SGUS034F February   2001  – June 2015 SMJ320VC33

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Description (continued)
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Recommended Operating Conditions
    3. 6.3  Electrical Characteristics
    4. 6.4  Phase-Locked Loop Characteristics Using EXTCLK or On-Chip Crystal Oscillator Timing Requirements
    5. 6.5  Circuit Parameters for On-Chip Crystal Oscillator Timing Requirements
    6. 6.6  Timing Requirements for EXTCLK, All Modes
    7. 6.7  Timing Requirements for Memory Read/Write for STRB
    8. 6.8  Timing Requirements for XF0 and XF1 when Executing LDFI or LDII
    9. 6.9  Timing Requirements for XF0 and XF1 when Executing SIGI
    10. 6.10 Timing Requirements for Changing XFx from Output to Input Mode
    11. 6.11 Timing Requirements for RESET
    12. 6.12 Timing Requirements for INT3 to INT0 Response
    13. 6.13 Timing Requirements for Serial Port
    14. 6.14 Timing Requirements for HOLD/HOLDA
    15. 6.15 Timing Requirements for Peripheral Pin General-Purpose I/O
    16. 6.16 Timing Requirements for Timer Pin
    17. 6.17 Timing Requirements for IEEE-1149.1 Test Access Port
    18. 6.18 Switching Characteristics for EXTCLK, All Modes
    19. 6.19 Switching Characteristics for Memory Read/Write for STRB
    20. 6.20 Switching Characteristics for XF0 and XF1 when Executing LDFI or LDII
    21. 6.21 Switching Characteristics for XF0 when Executing STFI or STII
    22. 6.22 Switching Characteristics for XF0 and XF1 when Executing SIGI
    23. 6.23 Switching Characteristics for Loading when XF is Configured as an Output
    24. 6.24 Switching Characteristics for Changing XFx from Output to Input Mode
    25. 6.25 Switching Characteristics for Changing XFx from an Input to an Output
    26. 6.26 Switching Characteristics for RESET
    27. 6.27 Switching Characteristics for IACK
    28. 6.28 Switching Characteristics for Serial Port
    29. 6.29 Switching Characteristics for HOLD/HOLDA
    30. 6.30 Switching Characteristics for Peripheral Pin General-Purpose I/O
    31. 6.31 Switching Characteristics for Timer Pin
    32. 6.32 Switching Characteristics for SHZ
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  JTAG Scan-Based Emulation Logic
      2. 8.2.2  Clock Generator
      3. 8.2.3  PLL and Clock Oscillator Control
      4. 8.2.4  PLL Isolation
      5. 8.2.5  Clock and PLL Considerations on Initialization
      6. 8.2.6  EDGEMODE
      7. 8.2.7  Reset Operation
      8. 8.2.8  PAGE0 to PAGE3 Select Lines
      9. 8.2.9  Using External Logic With the READY Pin
      10. 8.2.10 Posted Writes
      11. 8.2.11 Data Bus I/O Buffer
      12. 8.2.12 Bootloader Operation
      13. 8.2.13 JTAG Emulation
      14. 8.2.14 Designing a Target System Emulator Connector (14-Pin Header)
      15. 8.2.15 JTAG Emulator Cable Pod Logic
      16. 8.2.16 Reset Timing
      17. 8.2.17 Interrupt Response TIming
      18. 8.2.18 Interrupt-Acknowledge Timing
      19. 8.2.19 Data-Rate Timing Modes
      20. 8.2.20 HOLD Timing
      21. 8.2.21 General-Purpose I/O Timing
      22. 8.2.22 Peripheral Pin I/O Timing
      23. 8.2.23 Timer Pin Timing
    3. 8.3 Register Maps
  9. 9 Power Supply Recommendations
    1. 9.1 Power Sequencing Considerations
  10. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Timing Parameter Symbology
      2. 10.2.2 Device and Development-Support Tool Nomenclature
    3. 10.3 Related Links
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HFG|164
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
CVDD Supply voltage (2) –0.3 2.4 V
DVDD –0.3 4
VI Input voltage(3) –1 4.6
VO Output voltage –0.3 4.6
Continuous power dissipation (worst case)(4) 500 mW
TC Operating case temperature –55 125 °C
Tstg Storage temperature –55 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
(3) Absolute dc input level should not exceed the DVDD or VSS supply rails by more than 0.3 V. An instantaneous low current pulse of <2 ns, <10 mA, and <1 V amplitude is permissible.
(4) Actual operating power is much lower. This value was obtained under specially produced worst-case test conditions for the SMx320VC33, which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to the external data and address buses at the maximum possible rate with a capacitive load of 30 pF. See normal (ICC) current specification in Electrical Characteristics and also read TMS320C3x General-Purpose Applications (SPRU194).

6.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)(3)(4)
MIN NOM MAX UNIT
CVDD Supply voltage for the core CPU(5) 1.71 1.8 1.89 V
DVDD Supply voltage for the I/O pins(6) 3.14 3.3 3.46 V
VSS Supply ground 0 V
VIH High-level input voltage 0.7 x DVDD DVDD + 0.3(2) V
VIL Low-level input voltage –0.3(2) 0.3 x DVDD V
IOH High-level output current 4 mA
IOL Low-level output current 4 mA
CL Capacitive load per output pin 30 pF
TC Operating case temperature –55 125 °C
(1) All voltage values are with respect to VSS.
(2) Absolute dc input level should not exceed the DVDD or VSS supply rails by more than 0.3 V. An instantaneous low current pulse of <2 ns, <10 mA, and <1 V amplitude is permissible.
(3) All inputs and I/O pins are configured as inputs.
(4) All input and I/O pins use a Schmidt hysteresis inputs except SHZ and D0 to D31. Hysteresis is approximately 10% of DVDD and is centered at 0.5 × DVDD.
(5) CVDD should not exceed DVDD by more than 0.7 V. (Use a Schottky clamp diode between these supplies.)
(6) DVDD should not exceed CVDD by more than 2.5 V.

6.3 Electrical Characteristics

over recommended ranges of supply voltage (unless otherwise noted)(2)
PARAMETER TEST CONDITIONS(3) MIN TYP(4) MAX UNIT
VOH High-level output voltage DVDD = MIN, IOH = MAX 2.4 V
VOL Low-level output voltage DVDD = MIN, IOL = MAX 0.4 V
IZ High-impedance current TC = 25°C, DVDD = MAX –5 5 μA
II Input current TC = 25°C, VI = VSS to DVDD –5 5 μA
IIPU Input current (with internal pullup) Inputs with internal pullups(5) –600 10 μA
IIPD Input current (with internal pulldown) Inputs with internal pulldowns(5) 600 10 μA
IBKU Input current (with bus keeper) pullup(6) Bus keeper opposes until conditions match –600 10 μA
IBKD Input current (with bus keeper) pulldown(6) TC = 25°C, ƒx = 75 MHz 600 10 μA
IDDD Supply current, pins(7)(8) DVDD = MAX 25 260 mA
IDDC Supply current, core CPU(7)(8) TC = 25°C, ƒx = 75 MHz, CVDD = MAX 60 215 mA
IDD IDLE2, Supply current IDDD plus IDDC PLL enabled, oscillator enabled 2 mA
PLL disabled, oscillator enabled 500 μA
PLL disabled, oscillator disabled, FCLK = 0 50
Ci Input capacitance All inputs except XIN 10(1) pF
XIN 10(1)
Co Output capacitance 10(1) pF
(1) Not production tested
(2) All voltage values are with respect to VSS.
(3) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in Recommended Operating Conditions.
(4) For VC33, all typical values are at DVDD = 3.3, CVDD = 1.8 V, TC (case temperature) = 25°C.
(5) Pins with internal pullup devices: TDI, TCK, and TMS. Pin with internal pulldown device: TRST.
(6) Pins D0 to D31 include internal bus keepers that maintain valid logic levels when the bus is not driven (see Figure 30).
(7) Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test conditions, which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern at the maximum rate possible. See TMS320C3x General-Purpose Applications (SPRU194).
(8) ƒx is the PLL output clock frequency.

6.4 Phase-Locked Loop Characteristics Using EXTCLK or On-Chip Crystal Oscillator Timing Requirements

see (2)(3)
MIN MAX UNIT
Fpllin Frequency range, PLL input 5(1) 15(1) MHz
Fpllout Frequency range, PLL output 25(1) 75(1) MHz
Ipll PLL current, CVDD supply 2(1) mA
Ppll PLL power, CVDD supply 5(1) mW
PLLdc PLL output duty cycle at H1 45%(1) 55%(1)
PLLJ PLL output jitter, Fpllout = 25 MHz 400(1) ps
PLLLOCK PLL lock time in input cycles 1000 cycles
(1) Not production tested
(2) Duty cycle is defined as 100 × t1 / (t1 + t2)%
(3) To ensure clean internal clock references, the minimal low and high pulse durations must be maintained. At high frequencies, this may require a fast rise and fall time as well as a tightly controlled duty cycle. At lower frequencies, these requirements are less restrictive when in x1 and x0.5 modes. The PLL, however, must have an input duty cycle of between 40% and 60% for proper operation.

6.5 Circuit Parameters for On-Chip Crystal Oscillator Timing Requirements

see Figure 2(2)
MIN TYP MAX UNIT
VO Oscillator internal supply voltage CVDD V
FO Fundamental mode frequency range 1(1) 20(1) MHz
Vbias DC bias point (input threshold) 40(1) 50 60(1) %VO
Rfbk Feedback resistance 100(1) 300 500(1) kΩ
Rout Small signal ac output impedance 250(1) 500 1000(1) Ω
Vxoutac The ac output voltage with test crystal(3) 85 %VO
Vxinac The ac input voltage with test crystal(3) 85 %VO
Vxoutl Vxin = Vxinh, Ixout = 0, FO = 0 (logic input) VSS – 0.1(1) VSS + 0.3(1) V
Vxouth Vxin = Vxinl, Ixout = 0, FO = 0 (logic input) CVDD – 0.3(1) CVDD + 0.1(1) V
Vinl When used for logic level input, oscillator enabled –0.3(1) 0.2 × VO(1) V
Vinh When used for logic level input, oscillator enabled 0.8 × VO(1) DVDD + 0.3(1) V
Vxinh When used for logic level input, oscillator disabled 0.7 × DVDD DVDD + 0.3 V
Cxout XOUT internal load capacitance 2(1) 3 5(1) pF
Cxin XIN internal load capacitance 2(1) 3 5(1) pF
td(XIN-H1) Delay time, XIN to H1 x1 and x0.5 modes 2 5.5 8 ns
Iinl Input current, feedback enabled, Vil = 0 50(1) μA
Iinh Input current, feedback enabled, Vil = Vih –50(1) μA
(1) Not production tested
(2) This circuit is intended for series resonant fundamental mode operation.
(3) Signal amplitude is dependent on the crystal and load used.

6.6 Timing Requirements for EXTCLK, All Modes

see Figure 3 and Figure 4
MIN MAX UNIT
tr(EXTCLK) Rise time, EXTCLK F = Fmax, x0.5 and x1 modes 1(1) ns
F < Fmax 4(1)
tf(EXTCLK) Fall time, EXTCLK F = Fmax, x0.5 and x1 modes 1(1) ns
F < Fmax 4(1)
tw(EXTCLKL) Pulse duration, EXTCLK low x5 mode 21(1) ns
x1 mode 6(1)
x0.5 mode 4(1)
tw(EXTCLKH) Pulse duration, EXTCLK high x5 mode 21(1) ns
x1 mode 5(1)
x0.5 mode 4(1)
tdc(EXTCLK) Duty cycle, EXTCLK [tw(EXTCLKH) / tc(H)] x5 PLL mode 40%(1) 60%(1)
x1 and x0.5 modes, F = max 45% 55%
x1 and x0.5 modes, F = 0 Hz 0%(1) 100%(1)
tc(EXTCLK) Cycle time, EXTCLK x5 mode 66.7(1) 200(1) ns
x1 mode 13.3
x0.5 mode 10(1)
Fext Frequency range, 1 / tc(EXTCLK) x5 mode 5(1) 15(1) MHz
x1 mode 0 75
x0.5 mode 0(1) 100(1)
(1) Not production tested

6.7 Timing Requirements for Memory Read/Write for STRB

see Figure 5 through Figure 7(2)
MIN MAX UNIT
tsu(D-H1L)R Setup time, data before H1 low (read) 5(1) ns
th(H1L-D)R Hold time, data after H1 low (read) –1(1)
tsu(RDY-H1H) Setup time, RDY before H1 high 5
th(H1H-RDY) Hold time, RDY after H1 high –1(1)
td(A-RDY) Delay time, address valid to RDY P – 6(1)(3)
tv(A-D) Valid time, data valid after address PAGEx, or STRB valid 0 wait state, CL = 30 pF 6(1)
1 wait state tc(H) + 6(1)
(1) Not production tested
(2) These timings assume a similar loading of 30 pF on all pins.
(3) P = tc(H) / 2 (when duty cycle equals 50%).

6.8 Timing Requirements for XF0 and XF1 when Executing LDFI or LDII

see Figure 8
MIN MAX UNIT
tsu(XF1-H1L) Setup time, XF1 before H1 low 4(1) ns
th(H1L-XF1) Hold time, XF1 after H1 low 0(1)
(1) Not production tested

6.9 Timing Requirements for XF0 and XF1 when Executing SIGI

see Figure 10
MIN MAX UNIT
tsu(XF1-H1L) Setup time, XF1 before H1 low 4(1) ns
th(H1L-XF1) Hold time, XF1 after H1 low 0(1)
(1) Not production tested

6.10 Timing Requirements for Changing XFx from Output to Input Mode

see Figure 12
MIN MAX UNIT
tsu(XF-H1L) Setup time, XFx before H1 low 4 ns
th(H1L-XF) Hold time, XFx after H1 low 0

6.11 Timing Requirements for RESET

MIN MAX UNIT
tsu(RESET-EXTCLKL) Setup time, RESET before EXTCLK low 5(1) P – 7(1)(2) ns
tsu(RESETH-H1L) Setup time, RESET high before H1 low and after ten H1 clock cycles 5
(1) Not production tested
(2) P = tc(EXTCLK)

6.12 Timing Requirements for INT3 to INT0 Response

see Figure 15
MIN NOM MAX UNIT
tsu(INT-H1L) Setup time, INT3 to INT0 before H1 low 4(1) ns
th(H1L-INT) Hold time, INT3 to INT0 after H1 low 0
tw(INT) Pulse duration, interrupt to ensure only one interrupt P + 5(1)(2) 1.5P 2P - 5(1)(2)
(1) Not production tested
(2) P = tc(H)

6.13 Timing Requirements for Serial Port

see Figure 34 and Figure 35
MIN MAX UNIT
tc(SCK) Cycle time, CLKX/R CLKX/R ext tc(H) x 2.6(1) ns
CLKX/R int tc(H) x 4(1)(2) tc(H) × 216(1)
tw(SCK) Pulse duration, CLKX/R high/low CLKX/R ext tc(H) + 5
CLKX/R int [tc(SCK) / 2] - 4(1) [tc(SCK) / 2] + 4(1)
tr(SCK) Rise time, CLKX/R 3(1)
tf(SCK) Fall time, CLKX/R 3(1)
tsu(DR-CLKRL) Setup time, DR before CLKR low CLKR ext 4(1)
CLKR int 5(1)
th(CLKRL-DR) Hold time, DR after CLKR low CLKR ext 3(1)
CLKR int 0(1)
tsu(FSR-CLKRL) Setup time, FSR before CLKR low CLKR ext 4(1)
CLKR int 5(1)
th(SCKL-FS) Hold time, FSX/R input after CLKX/R low CLKX/R ext 3(1)
CLKX/R int 0(1)
tsu(FSX-CLKX) Setup time, external FSX before CLKX CLKX ext –[tc(H) – 6](1) [tc(SCK) / 2] - 6
CLKX int –[tc(H) - 10](1) tc(SCK) / 2(1)
(1) Not production tested
(2) A cycle time of tc(H) × 2 is possible when the device is operated at lower CPU frequencies. See the TMS320VC33 Silicon Update (SPRZ176) for further details.

6.14 Timing Requirements for HOLD/HOLDA

see Figure 17 and Figure 18
MIN MAX UNIT
tsu(HOLD-H1L) Setup time, HOLD before H1 low 3 ns
tw(HOLD) Pulse duration, HOLD low 3tc(H)(1)
(1) Not production tested.

6.15 Timing Requirements for Peripheral Pin General-Purpose I/O

see Figure 19 and Figure 20(2)
MIN MAX UNIT
tsu(GPIO-H1L) Setup time, general-purpose input before H1 low 3(1) ns
th(H1L-GPIO) Hold time, general-purpose input after H1 low 0(1)
(1) Not production tested
(2) Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents of internal-control registers associated with each peripheral.

6.16 Timing Requirements for Timer Pin

see Figure 21 and Figure 22(2)
MIN MAX UNIT
tsu(TCLK-H1L)(3) Setup time, TCLK external before H1 low 3(1) ns
th(H1L-TCLK)(3) Hold time, TCLK external after H1 low 0
(1) Not production tested
(2) Valid logic-level periods and polarity are specified by the contents of the internal control registers.
(3) These requirements are applicable for a synchronous input clock.

6.17 Timing Requirements for IEEE-1149.1 Test Access Port

see Figure 24
MIN MAX UNIT
tsu(TMS-TCKH) Setup time, TMS/TDI to TCK high 5(1) ns
th(TCKH-TMS) Hold time, TMS/TDI from TCK high 5(1) ns
td(TCKL-TDOV) Delay time, TCK low to TDO valid 0(1) 10(1) ns
tr (TCK) Rise time, TCK 3(1) ns
tf (TCK) Fall time, TCK 3(1) ns
(1) Not production tested

6.18 Switching Characteristics for EXTCLK, All Modes

over recommended operating conditions, all modes (see Figure 3 and Figure 4)
PARAMETER MIN TYP MAX UNIT
Vmid Midlevel, used to measure duty cycle 0.5 × DVDD V
td(EXTCLK-H) Delay time, EXTCLK to H1 and H3 x1 mode 2(1) 4.5 7(1) ns
x0.5 mode 2(1) 4.5 7(1)
tr(H) Rise time, H1 and H3 3(1) ns
tf(H) Fall time, H1 and H3 3(1) ns
td(HL-HH) Delay time, from H1 low to H3 high or from H3 low to H1 high –1.5(1) 2(1) ns
tc(H) Cycle time, H1 and H3 x5 PLL mode 1 / (5 × ƒext) ns
x1 mode 1 / ƒext
x0.5 mode 2 / ƒext
(1) Not production tested

6.19 Switching Characteristics for Memory Read/Write for STRB

over recommended operating conditions for memory read/write(2) (see Figure 5 through Figure 7)
PARAMETER MIN MAX UNIT
td(H1L-SL) Delay time, H1 low to STRB low –1(1) 3 ns
td(H1L-SH) Delay time, H1 low to STRB high –1(1) 3
td(H1H-RWL)W Delay time, H1 high to R/W low (write) –1(1) 3
td(H1L-A) Delay time, H1 low to address valid –1(1) 3
td(H1H-RWH)W Delay time, H1 high to R/W high (write) –1(1) 3
td(H1H-A)W Delay time, H1 high to address valid on back-to-back write cycles (write) –1(1) 3(1)
tv(H1L-D)W Valid time, data after H1 low (write) 5
th(H1H-D)W Hold time, data after H1 high (write) 0(1) 5
(1) Not production tested
(2) These timings assume a similar loading of 30 pF on all pins.

6.20 Switching Characteristics for XF0 and XF1 when Executing LDFI or LDII

over recommended operating conditions for XF0 and XF1 when executing LDFI or LDII (see Figure 8)
PARAMETER MIN MAX UNIT
td(H3H-XF0L) Delay time, H3 high to XF0 low 3 ns

6.21 Switching Characteristics for XF0 when Executing STFI or STII

over recommended operating conditions for XF0 when executing STFI or STII (see Figure 9)
PARAMETER MIN MAX UNIT
td(H3H-XF0H) Delay time, H3 high to XF0 high(1) 3 ns
(1) XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of the store is also driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store from executing, the address of the store will not be driven until the store can execute.

6.22 Switching Characteristics for XF0 and XF1 when Executing SIGI

over recommended operating conditions for XF0 and XF1 when executing SIGI (see Figure 10)
PARAMETER MIN MAX UNIT
td(H3H-XF0L) Delay time, H3 high to XF0 low 3 ns
td(H3H-XF0H) Delay time, H3 high to XF0 high 3

6.23 Switching Characteristics for Loading when XF is Configured as an Output

over recommended operating conditions for loading the XF register when configured as an output pin (see Figure 11)
MIN MAX UNIT
tv(H3H-XF) Valid time, XFx after H3 high 3 ns

6.24 Switching Characteristics for Changing XFx from Output to Input Mode

over recommended operating conditions for changing XFx from output to input mode (see Figure 12)
PARAMETER MIN MAX UNIT
tdis(H3H-XF) Disable time, XFx after H3 high 5(1) ns
(1) Not production tested

6.25 Switching Characteristics for Changing XFx from an Input to an Output

over recommended operating conditions for changing XFx from input to output mode (see Figure 13)
PARAMETER MIN MAX UNIT
td(H3H-XF) Delay time, H3 high to XFx switching from input to output 3 ns

6.26 Switching Characteristics for RESET

over recommended operating conditions for RESET (see Figure 14)
PARAMETER MIN(1) MAX(1) UNIT
td(EXTCLKH-H1H) Delay time, EXTCLK high to H1 high 2 7 ns
td(EXTCLKH-H1L) Delay time, EXTCLK high to H1 low 2 7
td(EXTCLKH-H3L) Delay time, EXTCLK high to H3 low 2 7
td(EXTCLKH-H3H) Delay time, EXTCLK high to H3 high 2 7
tdis(H1H-DZ) Disable time, data (high impedance) from H1 high(2) 6
tdis(H3H-AZ) Disable time, address (high impedance) from H3 high 6
td(H3H-CONTROLH) Delay time, H3 high to control signals high 3
td(H1H-RWH) Delay time, H1 high to R/W high 3
td(H1H-IACKH) Delay time, H1 high to IACK high 3
tdis(RESETL-ASYNCH) Disable time, asynchronous reset signals disabled (high impedance) from RESET low(3) 6
(1) Not production tested
(2) High impedance for Dbus is limited to nominal bus keeper ZOUT = 15 kΩ.
(3) Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.

6.27 Switching Characteristics for IACK

over recommended operating conditions for IACK (see Figure 16)
PARAMETER MIN MAX UNIT
td(H1H-IACKL) Delay time, H1 high to IACK low –1(1) 3 ns
td(H1H-IACKH) Delay time, H1 high to IACK high –1(1) 3
(1) Not production tested

6.28 Switching Characteristics for Serial Port

over recommended operating conditions (see Figure 34 and Figure 35)
PARAMETER MIN MAX UNIT
td(H1H-SCK) Delay time, H1 high to internal CLKX/R 4(1) ns
td(CLKX-DX) Delay time, CLKX to DX valid CLKX ext 6
CLKX int 5(1)
td(CLKX-FSX) Delay time, CLKX to internal FSX high/low CLKX ext 5
CLKX int 4(1)
td(CLKX-DX)V Delay time, CLKX to first DX bit, FSX precedes CLKX high CLKX ext 4
CLKX int 5(1)
td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 6
tdis(CLKX-DXZ) Disable time, DX high impedance following last data bit from CLKX high 6
(1) Not production tested

6.29 Switching Characteristics for HOLD/HOLDA

over recommended operating conditions for HOLD/HOLDA (see Figure 17 and Figure 18)
PARAMETER MIN MAX UNIT
tv(H1L-HOLDA) Valid time, HOLDA after H1 low –1(1) 3(1) ns
tw(HOLDA) Pulse duration, HOLDA low 2tc(H) – 4(1)
td(H1L-SH)H Delay time, H1 low to STRB high for a HOLD –1 3
tdis(H1L-S) Disable time, STRB to the high-impedance state from H1 low 4
ten(H1L-S) Enable time, STRB enabled (active) from H1 low 4
tdis(H1L-RW) Disable time, R/W to the high-impedance state from H1 low 5(1)
ten(H1L-RW) Enable time, R/W enabled (active) from H1 low 4
tdis(H1L-A) Disable time, address to the high-impedance state from H1 low 4(1)
ten(H1L-A) Enable time, address enabled (valid) from H1 low 5
tdis(H1H-D) Disable time, data to the high-impedance state from H1 high 4(1)
(1) Not production tested.

6.30 Switching Characteristics for Peripheral Pin General-Purpose I/O

over recommended operating conditions for peripheral pin general-purpose I/O (see Figure 19 and Figure 20)(1)
PARAMETER MIN MAX UNIT
td(H1H-GPIO) Delay time, H1 high to general-purpose output 4 ns
tdis(H1H) Disable time, general-purpose output from H1 high 5
(1) Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents of internal-control registers associated with each peripheral.

6.31 Switching Characteristics for Timer Pin

over recommended operating conditions for timer pin (see Figure 21 and Figure 22)
PARAMETER MIN MAX UNIT
td(H1H-TCLK) Delay time, H1 high to TCLK internal valid 3 ns
tc(TCLK)(2) Cycle time, TCLK TCLK ext tc(H) × 2.6(1)
TCLK int tc(H) × 2(1) tc(H) × 232(1)
tw(TCLK)(2) Pulse duration, TCLK TCLK ext tc(H) + 5(1)
TCLK int [tc(TCLK) / 2] - 4(1) [tc(TCLK) / 2] + 4(1)
(1) Not production tested
(2) These parameters are applicable for an asynchronous input clock.

6.32 Switching Characteristics for SHZ

over recommended operating conditions for SHZ (see Figure 23)
PARAMETER MIN MAX UNIT
tdis(SHZ) Disable time, SHZ low to all outputs, I/O pins disabled (high impedance) 0(1) 8(1) ns
(1) Not production tested