SCLS258N December   1995  – July 2024 SN54AHC138 , SN74AHC138

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Recommended Operating Conditions
    3. 4.3 Thermal Information
    4. 4.4 Electrical Characteristics
    5. 4.5 Switching Characteristics: VCC = 3.3V ± 0.3V
    6. 4.6 Switching Characteristics: VCC = 5V ± 0.5V
    7. 4.7 Operating Characteristics
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Function Table
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Links
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • W|16
  • J|16
  • FK|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

The SNx4AHC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

Device Information
PART NUMBER PACKAGE (1) PACKAGE SIZE (2) BODY SIZE (3)
SN74AHC138 RGY (VQFN, 16) 4mm x 3.5mm 4mm x 3.5mm
N (PDIP, 16) 19.3mm × 9.4mm 19.32mm x 6.35 mm
D (SOIC, 16) 9.9mm × 6mm 9.90mm x 3.90mm
NS (SOP, 16) 10.2mm x 7.8mm 10.20mm x 5.30mm
DB (SSOP, 16) 6.2mm × 7.8mm 6.20mm x 5.30mm
PW (TSSOP , 16) 5mm × 6.4mm 5.00mm x 4.40mm
DGV (TVSOP, 16) 3.6mm x 6.4mm 3.6mm x 4.4mm
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
SN54AHC138 SN74AHC138 Logic Diagram (Positive Logic) Logic Diagram (Positive Logic)