SCLS376J June   1997  – July 2024 SN54AHC273 , SN74AHC273

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements, VCC = 3.3 V ± 0.3 V
    7. 5.7  Timing Requirements, VCC = 5 V ± 0.5 V
    8. 5.8  Switching Characteristics, VCC = 3.3 V ± 0.3 V
    9. 5.9  Switching Characteristics, VCC = 5 V ± 0.5 V
    10. 5.10 Noise Characteristics
    11. 5.11 Operating Characteristics
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Links
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • W|20
  • J|20
  • FK|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

These devices are positive-edge-triggered D-type
flip-flops with a direct clear ( CLR) input.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.

Device Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
SNx4AHC273 N (PDIP, 20) 24.33mm x 9.4mm 25.40mm x 6.35mm
DB (SSOP, 20) 7.2mm × 7.8mm 7.50mm x 5.30mm
NS (SOP, 20) 12.60mm x 7.8mm 12.6mm x 5.30mm
PW (TSSOP, 20) 6.50mm × 6.4mm 6.50mm x 4.40mm
DGV (TVSOP, 20) 5.00mm x 6.4mm 5.00mm x 4.40mm
DW (SOIC, 20) 12.80mm × 10.3mm 12.8mm x 7.5mm
(1) For more information, see Section 11.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
SN54AHC273 SN74AHC273 Simplified SchematicsSimplified Schematics