SCLS247L October   1995  – February 2024 SN54AHC32 , SN74AHC32

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V
    7. 5.7 Switching Characteristics, VCC = 5 V ± 0.5 V
    8. 5.8 Noise Characteristics
    9. 5.9 Operating Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Standard CMOS Inputs
      2. 7.3.2 Balanced CMOS Push-Pull Outputs
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SNx4AHC32 devices are quadruple 2-input positive-OR gates. These devices perform the Boolean function Y = A × B or Y = A + B in positive logic.

Device Information
PART NUMBER RATING PACKAGE(1)
SN54AHC32 Military FK (LCCC, 20)
J (CDIP, 14)
W (CFP, 14)
SN74AHC32 Commercial DB (SSOP, 14)
DGV (TVSOP, 14)
D (SOIC, 14)
N (PDIP, 14)
NS (SO, 14)
PW (TSSOP, 14)
RGY (VQFN, 14)
BQA (WQFN, 14)
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-AC6C3D9D-F593-4B04-A224-6089D1845E7A-low.gifLogic Diagram (Positive Logic)