SCLS255N December   1995  – February 2024 SN54AHC74 , SN74AHC74

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information — SN74AHC74
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements — VCC = 3.3 V ± 0.3 V
    7. 5.7  Timing Requirements — VCC = 5 V ± 0.5 V
    8. 5.8  Switching Characteristics — VCC = 3.3 V ± 0.5 V
    9. 5.9  Switching Characteristics — VCC = 5 V ± 0.5 V
    10. 5.10 Noise Characteristics
    11. 5.11 Operating Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Considerations
        2. 8.2.1.2 Output Considerations
        3. 8.2.1.3 Power Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • J|14
  • FK|20
  • W|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-31871A61-72C7-45CA-B4B3-D5B7721C47DA-low.gifFigure 4-1 SN54AHC74 J or W Package,14-Pin CDIP or CFP(Top View)
GUID-31871A61-72C7-45CA-B4B3-D5B7721C47DA-low.gifFigure 4-2 SN74AHC74 D, DB, DGV, N, NS, or PW Package,14-Pin SOIC, SSOP, TVSOP, PDIP, SO, or TSSOP(Top View)
GUID-20201105-CA0I-R51S-5DRT-TCZRPR5P0NLB-low.gifFigure 4-3 SN74AHC74 RGY or BQA Package,14-Pin VQFN or WQFN With Exposed Thermal Pad(Top View)
GUID-20230616-SS0I-30VP-F16H-TQZVZL6MQTHB-low.gif
NC – No internal connection
Figure 4-4 SN54AHC74 FK Package,20-Pin LCCC(Top View)
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMECDIP or CFPSOIC, SSOP, TVSOP, PDIP, SO, or TSSOPVQFN, WQFNLCCC
1CLK3334

I

Clock for channel 1, rising edge triggered
1 CLR1112

I

Clear for channel 1, active low
1D2223

I

Data for channel 1
1 PRE4446

I

Preset for channel 1, active low
1Q5558

O

Output for channel 1
1 Q6669

O

Inverted output for channel 1
2CLK11111116

I

Clock for channel 2, rising edge triggered
2 CLR13131319

I

Clear for channel 2, active low
2D12121218

I

Data for channel 2
2 PRE10101014

I

Preset for channel 2, active low
2Q99913

O

Output for channel 2
2 Q88812

O

Inverted output for channel 2
GND77710—Ground
NC———1, 5, 7, 11, 15, 17—No internal connection
VCC14141420Positive supply
Thermal Pad—

Thermal Pad

(1) I = input, O = output