SCLS229L october   1995  – may 2023 SN54AHCT00 , SN74AHCT00

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Noise Characteristics
    8. 6.8 Operating Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS Push-Pull Outputs
      2. 8.3.2 TTL-Compatible CMOS Inputs
      3. 8.3.3 Clamp Diode Structure
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The ’AHCT00 devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

Package Information(1)
PART NUMBERPACKAGEBODY SIZE (NOM)
SN54AHCT00J (CDIP, 14)19.56 mm × 6.67 mm
W (CFP, 14)9.21 mm × 5.97 mm
FK (LCCC, 20)8.89 mm × 8.89 mm
SN74AHCT00D (SOIC , 14)8.65 mm × 3.91 mm
DB (SSOP, 14)6.20 mm × 5.30 mm
DGV (TVSOP, 14)3.60 mm × 4.40 mm
N (PDIP, 14)19.30 mm × 6.35 mm
NS (SOP, 14)10.30 mm × 5.30 mm
RGY (QFN, 14)3.50 mm × 3.50 mm
BQA (WQFN, 14)3.00 mm × 2.50 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-02A5AC4B-6030-4337-9C34-B3DDFAFFBBB4-low.png Logic Diagram, Each Gate (Positive Logic)