SCLS252O October   1995  – July 2024 SN54AHCT240 , SN74AHCT240

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Noise Characteristics
    8. 5.8 Operating Characteristics
    9. 5.9 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Links
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • W|20
  • J|20
  • FK|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Abstract

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

  • PRR ≤ 1 MHz
  • ZO = 50 Ω
  • tr ≤ 3 ns
  • tf ≤ 3 ns

Note:

All parameters and waveforms are not applicable to all devices.

SN54AHCT240 SN74AHCT240 Load Circuit For Totem-Pole Outputs
A. CL includes probe and jig capacitance.
B. The outputs are measured one at a time, with one transition per measurement.
Figure 6-1 Load Circuit For Totem-Pole Outputs
SN54AHCT240 SN74AHCT240 Load Circuit For Tri-State And Open-Drain Outputs
A. CL includes probe and jig capacitance.
B. The outputs are measured one at a time, with one transition per measurement.
Figure 6-2 Load Circuit For Tri-State And Open-Drain Outputs
Table 6-1 Loading Conditions For Parameter
TESTS1
tPLH(1), tPHL(1)Open
tPLZ(3), tPZL (2)VCC
tPHZ(3), tPZH(2)GND
Open drainVCC
(1) tPLH and tPHL are the same as tpd.
(2) tPZL and tPZH are the same as ten.
(3) tPLZ and tPHZ are the same as tdis.
SN54AHCT240 SN74AHCT240 Voltage Waveforms Pulse DurationsFigure 6-3 Voltage Waveforms Pulse Durations
SN54AHCT240 SN74AHCT240 Voltage Waveforms Propagation Delay Times Inverting and Noninverting Outputs
A. The outputs are measured one at a time, with one transition per measurement.
Figure 6-4 Voltage Waveforms Propagation Delay Times Inverting and Noninverting Outputs
SN54AHCT240 SN74AHCT240 Voltage Waveforms Setup And Hold TimesFigure 6-5 Voltage Waveforms Setup And Hold Times
SN54AHCT240 SN74AHCT240 Voltage Waveforms Enable And Disable Times Low- and High-Level Enabling
A. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
B. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 6-6 Voltage Waveforms Enable And Disable Times Low- and High-Level Enabling