Refer to the PDF data sheet for device specific package drawings
This device contains six independent inverters. Each gate performs the Boolean function Y = A in positive logic.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN74HC04D | SOIC (14) | 8.70 mm × 3.90 mm |
SN74HC04DB | SSOP (14) | 6.50 mm × 5.30 mm |
SN74HC04N | PDIP (14) | 19.30 mm × 6.40 mm |
SN74HC04NS | SO (14) | 10.20 mm × 5.30 mm |
SN74HC04PW | TSSOP (14) | 5.00 mm × 4.40 mm |
SN54HC04J | CDIP (14) | 21.30 mm × 7.60 mm |
SN54HC04W | CFP (14) | 9.20 mm × 6.29 mm |
SN54HC04FK | LCCC (20) | 8.90 mm × 8.90 mm |
Changes from Revision G (July 2015) to Revision H (April 2021)
Changes from Revision F (August 2013) to Revision G (July 2015)
Changes from Revision E (October 2010) to Revision F (August 2013)
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | D, DB, N, NS, PW, J, or W | FK | ||
1A | 1 | 2 | Input | Channel 1, Input A |
1Y | 2 | 3 | Output | Channel 1, Output Y |
2A | 3 | 4 | Input | Channel 2, Input A |
2Y | 4 | 6 | Output | Channel 2, Output Y |
3A | 5 | 8 | Input | Channel 3, Input A |
3Y | 6 | 9 | Output | Channel 3, Output Y |
GND | 7 | 10 | — | Ground |
4Y | 8 | 12 | Output | Channel 4, Output Y |
4A | 9 | 13 | Input | Channel 4, Input A |
5Y | 10 | 14 | Output | Channel 5, Output Y |
5A | 11 | 16 | Input | Channel 5, Input A |
6Y | 12 | 18 | Output | Channel 6, Output Y |
6A | 13 | 19 | Input | Channel 6, Input A |
VCC | 14 | 20 | — | Positive Supply |
NC | 1, 5, 7, 11, 15, 17 | — | Not internally connected |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Supply voltage | –0.5 | 7 | V | |
IIK | Input clamp current(2) | VI < 0 or VI > VCC | ±20 | mA | |
IOK | Output clamp current(2) | VO < 0 | ±20 | mA | |
IO | Continuous output current | VO = 0 to VCC | ±25 | mA | |
Continuous current through VCC or GND | ±50 | mA | |||
TJ | Junction temperature(3) | 150 | °C | ||
Tstg | Storage temperature | –60 | 150 | °C |