SCLS099I December   1982  – September 2024 SN54HC112 , SN74HC112

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions #GUID-2EBD0632-9121-4D73-88A3-4D53587EF83D/GUID-D459A9EC-CCFD-4DD4-8D23-57A07F876135
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements
    6. 5.6 Switching Characteristics
    7. 5.7 Operating Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Power Supply Recommendations
    2. 8.2 Layout
      1. 8.2.1 Layout Guidelines
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • W|16
  • J|16
  • FK|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt < 6ns.

For clock inputs, fmax is measured when the input duty cycle is 50%.

The outputs are measured one at a time with one input transition per measurement.

SN54HC112 SN74HC112 Load Circuit for Push-Pull Outputs
(1) CL includes probe and test-fixture capacitance.
Figure 6-1 Load Circuit for Push-Pull Outputs
SN54HC112 SN74HC112 Voltage Waveforms, Standard CMOS Inputs Pulse DurationFigure 6-2 Voltage Waveforms, Standard CMOS Inputs Pulse Duration
SN54HC112 SN74HC112 Voltage Waveforms, Propagation Delays for Standard CMOS Inputs
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4 Voltage Waveforms, Propagation Delays for Standard CMOS Inputs
SN54HC112 SN74HC112 Voltage Waveforms, Standard CMOS Inputs Setup and Hold TimesFigure 6-3 Voltage Waveforms, Standard CMOS Inputs Setup and Hold Times
SN54HC112 SN74HC112 Voltage Waveforms, Input and Output Transition Times for Standard CMOS Inputs
(1) The greater between tr and tf is the same as tt.
Figure 6-5 Voltage Waveforms, Input and Output Transition Times for Standard CMOS Inputs