3 Description

The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

Device Information

PART NUMBER	PACKAGE⁽¹⁾	BODY SIZE (NOM)
SN74HC138D	SOIC (16)	9.90 mm x 3.90 mm
SN74HC138DB	SSOP (16)	6.20 mm x 5.30 mm
SN74HC138N	PDIP (16)	19.32 mm x 6.35 mm
SN74HC138NS	SO (16)	10.20 mm x 5.30 mm
SN74HC138PW	TSSOP (16)	5.00 mm x 4.40 mm
SN54HC138J	CDIP (16)	21.34 mm x 6.92 mm
SN54HC138W	CFP (16)	10.16 mm x 6.73 mm
SN54HC138FK	LCCC (20)	8.89 mm x 8.89 mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.

Functional Block DIagram