SCLS116H December   1982  – December 2015 SN54HC165 , SN74HC165

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics, TA = 25°C
    6. 6.6  Electrical Characteristics, SN54HC165
    7. 6.7  Electrical Characteristics, SN74HC165
    8. 6.8  Switching Characteristics, TA = 25°C
    9. 6.9  Switching Characteristics, SN54HC165
    10. 6.10 Switching Characteristics, SN74HC165
    11. 6.11 Timing Requirements, TA = 25°C
    12. 6.12 Timing Requirements, SN54HC165
    13. 6.13 Timing Requirements, SN74HC165
    14. 6.14 Operating Characteristics
    15. 6.15 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Table
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
      1. 12.3.1 Trademarks
      2. 12.3.2 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • W|16
  • J|16
  • FK|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The SNx4HC165 is an 8-bit Parallel load shift register with 1 serial input and 8 parallel load input. The device loads all the 8 bits simultaneously through parallel load input when SH/LD is low. This will also ignore any input at CLK or CLK INH.

The device shifts the data when CLK toggles. The data is shifted on rising edge of the clock. Clock Inhibit (CLK INH) inhibits the clock function resulting in no change of the output. If SH/LD is low clock inputs are ignored. To realize the shift function, SH/LD should be high.

CLK and CLK INH functions are interchangeable. If CLK is low then change a clock signal at CLK INH pin causes a shift of data to QH. If CLK INH is Low clock signal on CLK pin shifts the data out to QH.

8.2 Functional Block Diagram

SN54HC165 SN74HC165 Logic.gif Figure 3. Logic Diagram Positive Logic
SN54HC165 SN74HC165 Typical_Shift.gif Figure 4. Typical Shift, Load, and Inhibit Sequence

8.3 Feature Description

The SNx4HC165 has a wide operating voltage range of 2 V to 6 V, outputs that can drive up to 10 LSTTL loads and Low Power Consumption, 80-μA maximum I. It is typically tpd = 13 ns and has ±4-mA output drive at 5 V with low input current of 1-μA maximum. The device features the direct overloading load of data input, meaning parallel data is loaded irrespective of clock signals.

8.4 Device Functional Table

Table 1 lists the functional modes of the SNx4HC165.

Table 1. Function Table

INPUTS FUNCTION
SH/LD CLK CLK INH
L X X Parallel load
H H X No change
H X H No change
H L ↑ Shift(1)
H ↑ L Shift(1)
(1) Shift : Content of each internal register shifts towards serial output QH. Data at SER is shifted into the first register