SCLS134F December   1982  – March 2022 SN54HC259 , SN74HC259

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions (1)
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements
    6. 5.6 Switching Characteristics
    7. 5.7 Operating Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • J|16
  • FK|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

These 8-bit addressable latches are designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches and being a 1-of-8 decoder or demultiplexer with active-high outputs.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
SN74HC259D SOIC (16) 9.90 mm × 3.90 mm
SN74HC259N PDIP (16) 19.31 mm × 6.35 mm
SN74HC259NS SO (16) 6.20 mm × 5.30 mm
SN74HC259PW TSSOP (16) 5.00 mm × 4.40 mm
SN54HC259J CDIP (16) 24.38 mm × 6.92 mm
SNJ54HC259FK LCCC (20) 8.89 mm × 8.45 mm
(1) For all available packages, see the orderable addendum at the end of the document.
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Pin numbers are for the D, J, N, NS, PW, and W packages.

Functional Block Diagram