SCLS310F January 1996 – June 2022 SN54HC368 , SN74HC368
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
These hex inverting buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC368 devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE and 2OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
SN54HC368J | CDIP (16) | 24.38 mm × 6.92 mm |
SN74HC368D | SOIC (16) | 9.90 mm × 3.90 mm |
SN74HC368N | PDIP (16) | 19.31 mm × 6.35 mm |
SN74HC368NS | SO (16) | 6.20 mm × 5.30 mm |
SN74HC368PW | TSSOP (16) | 5.00 mm × 4.40 mm |
SN54HC368FK | LCCC (20) | 8.89 mm × 8.45 mm |