Refer to the PDF data sheet for device specific package drawings
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the ’HC373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs.
PART NUMBER | PACKAGE(1) | BODY SIZE(2) |
---|---|---|
SN74HC373 | DW (SOIC, 20) | 12.80 mm × 7.50 mm |
DB (SSOP, 20) | 7.20 mm × 5.30 mm | |
N (PDIP, 20) | 25.40 mm × 6.35 mm | |
NS (SOP, 20) | 15.00 mm × 5.30 mm | |
PW (TSSOP, 20) | 6.50 mm × 4.40 mm | |
SN54HC373 | J (CDIP, 20) | 26.92 mm × 6.92 mm |
FK (LCCC, 20) | 8.89 mm × 8.45 mm | |
W (CFP, 20) | 13.72 mm × 6.92 mm |
PIN | TYPE1 | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
OE | 1 | Input | Output enable, active low |
1Q | 2 | Output | Output for channel 1 |
1D | 3 | Input | Input for channel 1 |
2D | 4 | Input | Input for channel 2 |
2Q | 5 | Output | Output for channel 2 |
3Q | 6 | Output | Output for channel 3 |
3D | 7 | Input | Input for channel 3 |
4D | 8 | Input | Input for channel 4 |
4Q | 9 | Output | Output for channel 4 |
GND | 10 | — | Ground |
LE | 11 | Input | Latch enable |
5Q | 12 | Output | Output for channel 5 |
5D | 13 | Input | Input for channel 5 |
6D | 14 | Input | Input for channel 6 |
6Q | 15 | Output | Output for channel 6 |
7Q | 16 | Output | Output for channel 7 |
7D | 17 | Input | Input for channel 7 |
8D | 18 | Input | Input for channel 8 |
8Q | 19 | Output | Output for channel 8 |
VCC | 20 | — | Positive supply |