SNx4LVC373A Octal Transparent D-Type Latches With 3-State Outputs
- SCAS295T January 1993 – July 2014 SN54LVC373A , SN74LVC373A
  
  PRODUCTION DATA.

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DATA SHEET

SNx4LVC373A Octal Transparent D-Type Latches With 3-State Outputs

1 Features

Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 6.8 ns at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
Supports Mixed-Mode Signal Operation
on All Ports
(5-V Input/Output Voltage With 3.3-V V_CC)
I_off Supports Live-Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.

2 Applications

Network Switches
TV Set-top Boxes
Motor Drives
PCs and Notebooks

3 Description

The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V V_CC operation, and the SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V V_CC operation.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
SNx4LVC373A	SSOP (20)	7.20 mm × 5.30 mm
	SOIC (20)	12.80 mm × 7.50 mm
	PDIP (20)	24.33 mm 6.35 mm
	TSSOP (20)	6.50 mm × 4.40 mm
	VQFN (20)	4.50 mm × 3.50 mm

For all available packages, see the orderable addendum at the end of the data sheet.

4 Simplified Schematic

5 Revision History

Changes from S Revision (May 2005) to T Revision

Updated document to new TI data sheet format.Go
Removed Ordering Information table.Go
Changed I_off Feature.Go
Added Military Disclaimer to Features.Go
Added Applications.Go
Added Handling Ratings table.Go
Changed MAX ambient temperature from 85°C to 125°C.Go
Added Thermal Information table.Go
Added Typical Characteristics. Go
Added Detailed Description section.Go

6 Pin Configuration and Functions

Pin Functions

PIN		I/O	DESCRIPTION
NO.	NAME	I/O	DESCRIPTION
1	OE	I	Enable Pin
2	1Q	O	Output 1
3	1D	I	Input 1
4	2D	I	Input 2
5	2Q	O	Output 2
6	3Q	O	Output 3
7	3D	I	Input 3
8	4D	I	Input 4
9	4Q	O	Output 4
10	GND	–	Ground Pin
11	LE	I	Latch Enable
12	5Q	O	Output 5
13	5D	I	Input 5
14	6D	I	Input 6
15	6Q	O	Output 6
16	7Q	O	Output 7
17	7D	I	Input 7
18	8D	I	Input 8
19	8Q	O	Output 8
20	VCC	–	Power Pin

Table 1. Pin Assignments

	1	2	3	4
A	1Q	OE	V_CC	8Q
B	2D	7D	1D	8D
C	3Q	2Q	6Q	7Q
D	4D	5D	3D	6D
E	GND	4Q	LE	5Q

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_CC	Supply voltage range		–0.5	6.5	V
V_I	Input voltage range⁽²⁾		–0.5	6.5	V
V_O	Voltage range applied to any output in the high-impedance or power-off state⁽²⁾		–0.5	6.5	V
V_O	Voltage range applied to any output in the high or low state⁽²⁾⁽³⁾		–0.5	V_CC + 0.5	V
I_IK	Input clamp current	V_I < 0		–50	mA
I_OK	Output clamp current	V_O < 0		–50	mA
I_O	Continuous output current			±50	mA
	Continuous current through V_CC or GND			±100	mA

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The value of V_CC is provided in the Recommended Operating Conditions table.

7.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–65	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	0	2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	0	1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			SN54LVC373A		SN74LVC373A		UNIT
			MIN	MAX	MIN	MAX	UNIT
V_CC	Supply voltage	Operating	2	3.6	1.65	3.6	V
V_CC	Supply voltage	Data retention only	1.5		1.5		V
V_IH	High-level input voltage	V_CC = 1.65 V to 1.95 V			0.65 × V_CC		V
		V_CC = 2.3 V to 2.7 V			1.7
		V_CC = 2.7 V to 3.6 V	2		2
V_IL	Low-level input voltage	V_CC = 1.65 V to 1.95 V				0.35 × V_CC	V
		V_CC = 2.3 V to 2.7 V				0.7
		V_CC = 2.7 V to 3.6 V		0.8		0.8
V_I	Input voltage		0	5.5	0	5.5	V
V_O	Output voltage	High or low state	0	V_CC	0	V_CC	V
V_O	Output voltage	3-state	0	5.5	0	5.5	V
I_OH	High-level output current	V_CC = 1.65 V				–4	mA
		V_CC = 2.3 V				–8
		V_CC = 2.7 V		–12		–12
		V_CC = 3 V		–24		–24
I_OL	Low-level output current	V_CC = 1.65 V				4	mA
		V_CC = 2.3 V				8
		V_CC = 2.7 V		12		12
		V_CC = 3 V		24		24
Δt/Δv	Input transition rise or fall rate			10		10	ns/V
T_A	Operating free-air temperature		–55	125	–40	125	°C

(1) All unused inputs of the device must be held at V_CCor GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, (SCBA004).

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		SN74LVC373A	UNIT
		PW
		20 PINS
R_θJA	Junction-to-ambient thermal resistance	102.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	35.9
R_θJB	Junction-to-board thermal resistance	53.5
ψ_JT	Junction-to-top characterization parameter	2.2
ψ_JB	Junction-to-board characterization parameter	52.9
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS		V_CC	SN54LVC373A			SN74LVC373A			UNIT
PARAMETER	TEST CONDITIONS		V_CC	MIN	TYP⁽¹⁾	MAX	MIN	TYP⁽¹⁾	MAX	UNIT
V_OH	I_OH = –100 µA		1.65 V to 3.6 V				V_CC – 0.2			V
	I_OH = –100 µA		2.7 V to 3.6 V	V_CC – 0.2
	I_OH = –4 mA		1.65 V				1.2
	I_OH = –8 mA		2.3 V				1.7
	I_OH = –12 mA		2.7 V	2.2			2.2
	I_OH = –12 mA		3 V	2.4			2.4
	I_OH = –24 mA		3 V	2.2			2.2
V_OL	I_OL = 100 µA		1.65 V to 3.6 V						0.2	V
	I_OL = 100 µA		2.7 V to 3.6 V			0.2
	I_OL = 4 mA		1.65 V						0.45
	I_OL = 8 mA		2.3 V						0.7
	I_OL = 12 mA		2.7 V			0.4			0.4
	I_OL = 24 mA		3 V			0.55			0.55
I_I	V_I = 0 to 5.5 V		3.6 V			±5			±5	µA
I_off	V_I or V_O = 5.5 V		0						±10	µA
I_OZ	V_O = 0 to 5.5 V		3.6 V			±15			±10	µA
I_CC	V_I = V_CC or GND	I_O = 0	3.6 V			10			10	µA
I_CC	3.6 V ≤ V_I ≤ 5.5 V⁽²⁾	I_O = 0	3.6 V			10			10	µA
ΔI_CC	One input at V_CC – 0.6 V, Other inputs at V_CC or GND		2.7 V to 3.6 V			500			500	µA
C_i	V_I = V_CC or GND		3.3 V		4	12		4		pF
C_o	V_O = V_CC or GND		3.3 V		5.5	12		5.5		pF

(1) All typical values are at V_CC = 3.3 V, T_A = 25°C.

(2) This applies in the disabled state only.

7.6 Timing Requirements, SN54LVC373A

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)

PARAMETER		SN54LVC373A				UNIT
		V_CC = 2.7 V		V_CC= 3.3 V ± 0.3 V
		MIN	MAX	MIN	MAX
t_w	Pulse duration, LE high	3.3		3.3		ns
t_su	Setup time, data before LE↓	2		2		ns
t_h	Hold time, data after LE↓	2		2		ns

7.7 Timing Requirements, SN74LVC373A

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)

PARAMETER		SN74LVC373A								UNIT
		V_CC= 1.8 V ± 0.15 V		V_CC= 2.5 V ± 0.2 V		V_CC = 2.7 V		V_CC= 3.3 V ± 0.3 V
		MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX
t_w	Pulse duration, LE high	9		4		3.3		3.3		ns
t_su	Setup time, data before LE↓	6		4		2		2		ns
t_h	Hold time, data after LE↓	4		2		1.5		1.5		ns

7.8 Switching Characteristics, SN54LVC373A

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)

PARAMETER	FROM (INPUT)	TO (OUTPUT)	SN54LVC373A				UNIT
			V_CC = 2.7 V		V_CC = 3.3 V ± 0.3 V
			MIN	MAX	MIN	MAX
t_pd	D	Q		8.5	1	7.5	ns
t_pd	LE	Q		9.5	1	8.5	ns
t_en	OE	Q		8.7	1	7.7	ns
t_dis	OE	Q		8	0.5	7	ns

7.9 Switching Characteristics, SN74LVC373A

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)

PARAMETER	FROM (INPUT)	TO (OUTPUT)	SN74LVC373A								UNIT
			V_CC = 1.8 V ± 0.15 V		V_CC = 2.5 V ± 0.2 V		V_CC = 2.7 V		V_CC = 3.3 V ± 0.3 V
			MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX
t_pd	D	Q	1	19.1	1	9.6		7.8	1.5	6.8	ns
t_pd	LE	Q	1	22.8	1	10.5		8.2	2	7.6	ns
t_en	OE	Q	1	20	1	10.5		8.7	1.5	7.7	ns
t_dis	OE	Q	1	19.3	1	7.8		7.6	1.5	7	ns
t_sk(o)				1		1		1		1	ns

7.10 Operating Characteristics

T_A= 25°C

PARAMETER			TEST CONDITIONS	V_CC = 1.8 V	V_CC = 2.5 V	V_CC = 3.3 V	UNIT
PARAMETER			TEST CONDITIONS	TYP	TYP	TYP	UNIT
C_pd	Power dissipation capacitance per latch	Outputs enabled	f = 10 MHz	61	56	46	pF
C_pd	Power dissipation capacitance per latch	Outputs disabled	f = 10 MHz	3	3	3	pF

7.11 Typical Characteristics

Figure 1. SN74LVC373A LE to Q TDP
V_CC vs TPD at 25°C

Figure 2. SN74LVC373A LE to Q
Across Temperature at 3.3-V V_CC

8 Parameter Measurement Information

Figure 3. Load Circuit and Voltage Waveforms

9 Detailed Description

9.1 Overview

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

9.2 Functional Block Diagram

9.3 Feature Description

Wide operating voltage range
- Operates from 1.65 V to 3.6 V
Allows down voltage translation
- Inputs accept voltages to 5.5 V
I_off feature
- Allows voltages on the inputs and outputs when V_CC is 0 V

9.4 Device Functional Modes

Table 2. Function Table (Each Latch)

INPUTS			OUTPUT Q
OE	LE	D	OUTPUT Q
L	H	H	H
L	H	L	L
L	L	X	Q₀
H	X	X	Z