SCAS992A March   2024  – January 2025 SN54SC8T595-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 SCxT Enhanced Input Voltage
        1. 7.3.1.1 Down Translation
        2. 7.3.1.2 Up Translation
      2. 7.3.2 Balanced CMOS 3-State Outputs
      3. 7.3.3 Balanced CMOS Push-Pull Outputs
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω.

For clock inputs, fmax is measured when the input duty cycle is 50%.

The outputs are measured one at a time with one input transition per measurement.

SN54SC8T595-SEP Load Circuit for 3-State Outputs
(1) CL includes probe and test-fixture capacitance.
Figure 6-1 Load Circuit for 3-State Outputs
SN54SC8T595-SEP Voltage Waveforms Propagation Delays
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-3 Voltage Waveforms Propagation Delays
SN54SC8T595-SEP Voltage Waveforms, Input and Output Transition Times
(1) The greater between tr and tf is the same as tt.
Figure 6-5 Voltage Waveforms, Input and Output Transition Times
SN54SC8T595-SEP Load Circuit for Push-Pull Outputs
(1) CL includes probe and test-fixture capacitance.
Figure 6-2 Load Circuit for Push-Pull Outputs
SN54SC8T595-SEP Voltage Waveforms Propagation Delays
(1) S1 = CLOSED, S2 = OPEN.
(2) S1 = OPEN, S2 = CLOSED.
(3) The greater between tPZL and tPZH is the same as ten.
(4) The greater between tPLZ and tPHZ is the same as tdis.
Figure 6-4 Voltage Waveforms Propagation Delays