Unless otherwise noted, all input
pulses are supplied by generators having the following characteristics:
- f =1 MHz
- Z0 = 50 Ω
- dv / dt ≤ 1 ns/V
![SN54SLC8T245-SEP Load
Circuit GUID-2D5AFCD0-BE3C-438B-9DB0-88EFF4CD907B-low.gif](/ods/images/SCES946B/GUID-2D5AFCD0-BE3C-438B-9DB0-88EFF4CD907B-low.gif)
A. CL
includes probe and jig capacitance.
Figure 6-1 Load
Circuit![SN54SLC8T245-SEP Load
Circuit Conditions GUID-6E0E7E00-3CAA-4ADC-9837-9D87E9EF423B-low.gif](/ods/images/SCES946B/GUID-6E0E7E00-3CAA-4ADC-9837-9D87E9EF423B-low.gif)
A. Output waveform on
the conditions that input is driven to a valid Logic Low.
B. Output waveform on
the condition that input is driven to a valid Logic High.
Figure 6-2 Load
Circuit Conditions
![SN54SLC8T245-SEP Propagation Delay GUID-F1C9D0DB-EEFA-4DA8-A176-D06E69C1ED0D-low.gif](/ods/images/SCES946B/GUID-F1C9D0DB-EEFA-4DA8-A176-D06E69C1ED0D-low.gif)
A. VCCI is the
supply pin associated with the input port.
B. VOH and
VOL are typical output voltage levels with specified
RL, CL, and S1.
Figure 6-3 Propagation Delay![SN54SLC8T245-SEP Enable Time And Disable Time GUID-FB9C9397-9694-4725-80CD-A85F48EAB93F-low.gif](/ods/images/SCES946B/GUID-FB9C9397-9694-4725-80CD-A85F48EAB93F-low.gif)
A. Output waveform
on the condition that input is driven to a valid Logic Low.
B. Output waveform
on the condition that input is driven to a valid Logic High.
C. VCCO is
the supply pin associated with the output port.
D. VOH and
VOL are typical output voltage levels with specified
RL, CL, and S1.
Figure 6-4 Enable Time And Disable Time