SLLSFI8 February   2021 SN55LVCP22A-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Select Pins
      2. 8.3.2 Output Enable Pins
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Current-Mode Logic (CML)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Single-Ended (LVPECL)
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
      4. 9.2.4 Low-Voltage Differential Signaling (LVDS)
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
      5. 9.2.5 Cold Sparing
      6. 9.2.6 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
CMOS/TTL DC SPECIFICATIONS (EN0, EN1, SEL0, SEL1)
VIH High-level input voltage 2 1.5 VCC V
VIL Low-level input voltage GND 1.5 0.8 V
IIH2 High-level input current VIN = 3.6 V or 2.0 V, VCC = 0 V -250 ±3 250 µA
IIH High-level input current VIN = 3.6 V or 2.0 V, VCC = 3.6 V -25 ±3 25 µA
IIL2 Low-level input current VIN = 0.0 V or 0.8 V, VCC = 0 V -150 ±1 150 µA
IIL Low-level input current VIN = 0.0 V or 0.8 V, VCC = 3.6 V -15 ±1 15 µA
VCL Input clamp voltage ICL = –18 mA -0.8 -1.5 V
LVDS OUTPUT SPECIFICATIONS (OUT0, OUT1)
|VOD| Differential output voltage RL = 75 Ω, See Figure 7-3 255 390 475 mV
RL = 75 Ω, VCC = 3.3 V, TA = 25°C, See Figure 7-3 320 390 430
Δ|VOD| Change in differential output voltage magnitude between logic states VID = ±100 mV, See Figure 7-3 –25 25 mV
VOS Steady-state offset voltage See Figure 7-4 1 1.2 1.45 V
ΔVOS Change in steady-state offset voltage between logic states See Figure 7-4 –25 25 mV
VOC(PP) Peak-to-peak common-mode output voltage See Figure 7-4 50 mV
IOZ High-impedance output current VOUT = GND or VCC -15 15 µA
IOFF Power-off leakage current VCC = 0 V, 1.5 V; VOUT = 3.6 V or GND -15 15 µA
IOZH High-impedance output current, after HDR 100 krad VOUT = VCC, TA = 25°C -120 350 µA
IOFFH Power-off leakage current, after  after HDR 100 krad VCC = 0 V, 1.5 V; VOUT = 3.6 V, TA = 25°C -50 150 µA
IOS Output short-circuit current VOUT+ or VOUT- = 0 V -8 mA
IOSB Both outputs short-circuit current VOUT+ and VOUT- = 0 V –8 8 mA
CO Differential output capacitance VI = 0.4 sin(4E6πt) + 0.5 V 3 pF
LVDS RECEIVER DC SPECIFICATIONS (IN0, IN1)
VTH Positive-going differential input voltage threshold See Figure 7-2 and Table 7-1 100 mV
VTL Negative-going differential input voltage threshold See Figure 7-2 and Table 7-1 –100 mV
VID(HYS) Differential input voltage hysteresis 20 150 mV
VCMR Common-mode voltage range VID = 100 mV, VCC = 3.0 V to 3.6 V 0.05 3.95 V
IIN Input current VIN = 4 V, VCC = 3.6 V or 0.0 -18 ±1 18 µA
VIN = 0 V, VCC = 3.6V or 0.0 -18 ±1 18
CIN Differential input capacitance VI = 0.4 sin (4E6πt) + 0.5 V 3 pF
SUPPLY CURRENT
ICCQ Quiescent supply current RL = 75 Ω, EN0=EN1=High 60 87 mA
ICCD Total supply current RL = 75 Ω, CL = 5 pF, 500 MHz (1000 Mbps), EN0=EN1=High 63 87 mA
ICCZ 3-state supply current EN0 = EN1 = Low 25 35 mA
(1) All typical values are at 25°C and with a 3.3-V supply.