SLLSFM1 September   2022 SN6507-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics, SN6507-Q1
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Push-Pull Converter
      2. 8.3.2 Core Magnetization
      3. 8.3.3 Duty Cycle Control
      4.      Programmable Switching Frequency
      5. 8.3.4 Spread Spectrum Clocking
      6. 8.3.5 Slew Rate Control
      7. 8.3.6 Protection Features
        1. 8.3.6.1 Over Voltage Protection (OVP)
        2. 8.3.6.2 Over Current and Short Circuit Protection (OCP)
        3. 8.3.6.3 Under Voltage Lock-Out (UVLO)
        4. 8.3.6.4 Thermal Shut Down (TSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-Up Mode
        1. 8.4.1.1 Soft-Start
      2. 8.4.2 Operation Mode
      3. 8.4.3 Shutdown Mode
      4. 8.4.4 SYNC Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Pin Configuration
        2. 9.2.2.2 LDO Selection
        3. 9.2.2.3 Diode Selection
        4. 9.2.2.4 Capacitor and Inductor Selection
        5. 9.2.2.5 Transformer Selection
          1. 9.2.2.5.1 V-t Product Calculation
          2. 9.2.2.5.2 Turns Ratio Estimate
        6. 9.2.2.6 Low-Emissions Designs
      3. 9.2.3 Application Curves
      4. 9.2.4 System Examples
        1. 9.2.4.1 Higher Output Voltage Designs
        2. 9.2.4.2 Commercially-Available Transformers
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.4 Capacitor and Inductor Selection

Capacitor Selection

The capacitors in the push-pull converter circuits are normally multi-layer ceramic chip (MLCC) capacitors. As with many high speed CMOS ICs, the device requires a bypass capacitor of 100 nF. Ensure this capacitor is placed within 2 mm of the SN6507-Q1 VCC pin.

The input bulk capacitor at the center-tap of the transformer primary side supports large currents into the primary winding during the fast switching transients. For minimum ripple make this capacitor 1 μF to 10 μF, where 10 μF is preferred. Place this capacitor close to the transformer primary winding center-tap to minimize trace inductance. If placed on the opposite side of the PCB from the transformer, an additional 100 nF capacitor can be placed on the same layer and close to the transformer center tap. Use two vias in parallel for each connection between these capacitors to the transformer center tap to ensure low-inductance paths.

The bulk capacitor at the rectifier output smooths the output voltage. Make this capacitor 500 nF to 10 μF. To avoid hitting OCP at the transistion from soft-start to steady state, the output capacitor COUT is recommended to be less than 10 times of CSS connected to the SS/ILIM pin. Otherwise, if there is a short soft-start time due to a small CSS value, the output capacitor is only partially charged and sees high current spikes on the first switching cycles after the device exits soft start mode.

Optional capacitors of values between 1 nF to 4.7 nF can be connected to the control pins of SN6507-Q1 for filtering if operating in noisy environments.

If an LDO is used, an additional small capacitor at the LDO input is not necessarily required. However, good analog design practice suggests using a small value of 47 nF to 100 nF improves the regulator’s transient response and noise rejection.

If an LDO is used, an additional capacitor at the LDO output buffers the regulated output supply for the subsequent isolator and transceiver circuitry. The choice of output capacitor depends on the LDO stability requirements specified in the data sheet. However, in most cases, a low-ESR ceramic capacitor in the range of 4.7 μF to 10 μF will satisfy these requirements.

Inductor Selection

The inductor is required only for duty cycle feature. The minimum inductor value (LMIN) is is calculated by Equation 2. Higher inductance produces better regulation and lower voltage ripple, but requires a correspondingly larger size inductor. The optimum inductor value is determined by taking into account the tradeoff between the regualtion performance and the size.

For example, when VOUT = 15 V, VIN TYP = 15 V, VIN MAX = 18 V, ILOAD MIN = 250 mA, fSW = 1 MHz, D = 0.25, the minimum inductance is calculated to be 50 μH.

Equation 8. LMIN=15V×1-2×0.25×(15V/18V)4×0.25A×1MHz=8.75μH