SLLSFM1 September   2022 SN6507-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics, SN6507-Q1
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Push-Pull Converter
      2. 8.3.2 Core Magnetization
      3. 8.3.3 Duty Cycle Control
      4.      Programmable Switching Frequency
      5. 8.3.4 Spread Spectrum Clocking
      6. 8.3.5 Slew Rate Control
      7. 8.3.6 Protection Features
        1. 8.3.6.1 Over Voltage Protection (OVP)
        2. 8.3.6.2 Over Current and Short Circuit Protection (OCP)
        3. 8.3.6.3 Under Voltage Lock-Out (UVLO)
        4. 8.3.6.4 Thermal Shut Down (TSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-Up Mode
        1. 8.4.1.1 Soft-Start
      2. 8.4.2 Operation Mode
      3. 8.4.3 Shutdown Mode
      4. 8.4.4 SYNC Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Pin Configuration
        2. 9.2.2.2 LDO Selection
        3. 9.2.2.3 Diode Selection
        4. 9.2.2.4 Capacitor and Inductor Selection
        5. 9.2.2.5 Transformer Selection
          1. 9.2.2.5.1 V-t Product Calculation
          2. 9.2.2.5.2 Turns Ratio Estimate
        6. 9.2.2.6 Low-Emissions Designs
      3. 9.2.3 Application Curves
      4. 9.2.4 System Examples
        1. 9.2.4.1 Higher Output Voltage Designs
        2. 9.2.4.2 Commercially-Available Transformers
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2 Core Magnetization

Figure 8-2 shows the ideal magnetizing curve for a push-pull converter with B as the magnetic flux density and H as the magnetic field strength. When Q1 conducts the magnetic flux is pushed from A to A’, and when Q2 conducts the flux is pulled back from A’ to A. The difference in flux and thus in flux density is proportional to the product of the primary voltage, VP, and the time, tON, it is applied to the primary: B ≈ VP × tON.

GUID-7AF16F9D-FABA-4A40-80CC-262BA3220AD4-low.gifFigure 8-2 Core Magnetization and Self-Regulation Through Positive Temperature Coefficient of RDS(on)

This volt-seconds (V-t) product is important as it determines the core magnetization during each switching cycle. If the V-t products of both phases are not identical, an imbalance in flux density swing results with an offset from the origin of the B-H curve. If balance is not restored, the offset increases with each following cycle and the transformer slowly creeps toward the saturation region.

Fortunately, due to the positive temperature coefficient of a MOSFET’s on-resistance, the output FETs of the SN6507-Q1 have a self-correcting effect on V-t imbalance. In the case of a slightly longer on-time, the prolonged current flow through a FET gradually heats the transistor which leads to an increase in RDS-on. The higher resistance then causes the drain-source voltage, VDS, to rise. Because the voltage at the primary is the difference between the constant input voltage, VIN, and the voltage drop across the MOSFET, VP = VIN – VDS, VPis gradually reduced and V-t balance restored.