SLLSFM1 September   2022 SN6507-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics, SN6507-Q1
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Push-Pull Converter
      2. 8.3.2 Core Magnetization
      3. 8.3.3 Duty Cycle Control
      4.      Programmable Switching Frequency
      5. 8.3.4 Spread Spectrum Clocking
      6. 8.3.5 Slew Rate Control
      7. 8.3.6 Protection Features
        1. 8.3.6.1 Over Voltage Protection (OVP)
        2. 8.3.6.2 Over Current and Short Circuit Protection (OCP)
        3. 8.3.6.3 Under Voltage Lock-Out (UVLO)
        4. 8.3.6.4 Thermal Shut Down (TSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-Up Mode
        1. 8.4.1.1 Soft-Start
      2. 8.4.2 Operation Mode
      3. 8.4.3 Shutdown Mode
      4. 8.4.4 SYNC Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Pin Configuration
        2. 9.2.2.2 LDO Selection
        3. 9.2.2.3 Diode Selection
        4. 9.2.2.4 Capacitor and Inductor Selection
        5. 9.2.2.5 Transformer Selection
          1. 9.2.2.5.1 V-t Product Calculation
          2. 9.2.2.5.2 Turns Ratio Estimate
        6. 9.2.2.6 Low-Emissions Designs
      3. 9.2.3 Application Curves
      4. 9.2.4 System Examples
        1. 9.2.4.1 Higher Output Voltage Designs
        2. 9.2.4.2 Commercially-Available Transformers
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Minimum and maximum limits apply over the recommended junction temperature range, unless otherwise indicated. All typical values are at TA = 25°C, VCC = 24 V,  CLK FSW = 1 MHz and VEN/UVLO=2.5 V unless otherwise stated.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
Icc VIN Supply Current (3 V < VCC < 36V) , not including switch drive currents VEN/UVLO=2.5 V, RL = 50 Ω 3 4 mA
ISHUTDOWN VIN shutdown current VEN/UVLO=0 V, RL = 50 Ω 0.8 2.5 µA
ILKG(SS/ILIM)  Leakage Current on SS/ILIM pin VEN/UVLO = 0 V, Voltage of SS/ILIM = 5 V 0.7 µA
ENABLE AND UVLO
VCCUVLO-RISING VCC Positive-going UVLO threshold  VCC rising , EN/UVLO is shorted to VCC 2.8 2.9 V
VCCUVLO-FALLING VCC Negative-going UVLO threshold VCC falling, EN/UVLO is shorted to VCC 2.5 2.67 V
VCCUVLO-HYS VCC UVLO threshold hysteresis EN/UVLO is shorted to VCC 0.1 0.12 V
ENUVLO-RISING EN/UVLO Positive-going UVLO threshold EN/UVLO rising 1.4 1.5 1.6 V
ENUVLO-FALLING EN/UVLO Negative-going UVLO threshold EN/UVLO falling  1.25 1.35 1.45 V
ENUVLO-HYS EN/UVLO UVLO threshold hysteresis 0.14 0.15 V
POWER STAGE
DMM Average ON time mismatch between SW1 and SW2 RL = 50 Ω to VCC, Figure 7-3 0 %
R(ON) Output switch ON resistance VCC = 24 V, ISW1, ISW2 = 0.5 A 0.45 1 Ω
V(SLEW) Voltage slew rates on SW1 and SW2 RL = 50 Ω to VCC, VCC = 12 V; RSR = 9.6 kΩ (Default), Figure 7-3 298 V/µs
V(SLEW) Voltage slew rates on SW1 and SW2 RL = 50 Ω to VCC, VCC = 12 V; RSR = 9.6 kΩ (Default), Figure 7-3 369 V/µs
CLK
FSW D1, D2 average switching Frequency (Default) RL = 50 Ω, RCLK = 0 kΩ, Figure 7-3 780 1000 1296 kHz
F(SYNC) External clock frequency on CLK pin External clock applied on CLK pin for SYNC mode. SW1/SW2 switches at 1/2 the external CLK frequency 200 4000 kHz
VCLK(High) CLK pin logic high threshold 1.6 1.8 V
VCLK(Low) CLK pin logic low threshold 1.0 1.2 V
SOFT-START
ISS SS ext capacitor charging current 275 µA
CSS Range SS ext capacitor range 0.05 5 µF
CURRENT LIMIT
ILIM SW1 and SW2 Current Limit RLIM = 18.2 kΩ, 5 V < VCC < 36 V 1.00 1.30 1.59 A
ILIM SW1 and SW2 Current Limit RLIM = 30.1 kΩ, 5 V < VCC < 36 V 0.56 0.79 1.02 A
ILIM SW1 and SW2 Current Limit RLIM = 261 kΩ, 5 V < VCC < 36 V 0.06 0.10 0.14 A
DC CONTROL
Dsw1, Dsw2 Switching Duty Cycle on SW1 and SW2 DC pin floating (Default), FSW = 300KHz, Figure 7-2 48 %
Dsw1, Dsw2 Switching Duty Cycle on SW1 and SW2 External CLK (SYNC mode), FSW = 300KHz, Figure 7-2 48 %
INPUT OVLO
VCCOVLO-RISING Input Over-voltage Lockout  Rising Threshold  VCC rising 36.9 38.7 40.5 V
VCCOVLO-FALLING Input Over-voltage Lockout Falling Threshold  VCC falling 36.5 38.2 40.0 V
VCCOVLO-HYS Input Over-voltage Lockout Hysteresis VCC hysteresis voltage 0.47 0.57 V
THERMAL SHUT DOWN
TSD+ TSD turn on temperature TJ rising 170 184 198 °C
TSD- TSD turn off temperature TJ falling 135 147 159 °C
TSD-HYST TSD hysteresis 32 37 42 °C