SLLSFM0A March   2022  – June 2022 SN6507

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics, SN6507
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Push-Pull Converter
      2. 8.3.2 Core Magnetization
      3. 8.3.3 Duty Cycle Control
      4.      Programmable Switching Frequency
      5. 8.3.4 Spread Spectrum Clocking
      6. 8.3.5 Slew Rate Control
      7. 8.3.6 Protection Features
        1. 8.3.6.1 Over Voltage Protection (OVP)
        2. 8.3.6.2 Over Current and Short Circuit Protection (OCP)
        3. 8.3.6.3 Under Voltage Lock-Out (UVLO)
        4. 8.3.6.4 Thermal Shut Down (TSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-Up Mode
        1. 8.4.1.1 Soft-Start
      2. 8.4.2 Operation Mode
      3. 8.4.3 Shutdown Mode
      4. 8.4.4 SYNC Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Pin Configuration
        2. 9.2.2.2 LDO Selection
        3. 9.2.2.3 Diode Selection
        4. 9.2.2.4 Capacitor and Inductor Selection
        5. 9.2.2.5 Transformer Selection
          1. 9.2.2.5.1 V-t Product Calculation
          2. 9.2.2.5.2 Turns Ratio Estimate
        6. 9.2.2.6 Low-Emissions Designs
      3. 9.2.3 Application Curves
      4. 9.2.4 System Examples
        1. 9.2.4.1 Higher Output Voltage Designs
        2. 9.2.4.2 Commercially-Available Transformers
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.5 Slew Rate Control

To allow optimization of EMI with respect to efficiency, the SN6507 is designed to allow a resistor (RSR) to select the strength of the driver of PowerFETs turning on. As shown in Figure 8-7 below, the slew rate of the switching edges is controllable with the resistor. Rolling off harmonics through slew rate control can eliminate the need for shielding and common mode chokes in many applications.

The EMI benefit of slew rate control may result in slightly reduced efficiency and higher peak current (ISW_SR). When the feature slows down the charging and discharging of the gate capacitance, the extended transition times of the FETs increases the transition losses during each switching cycle. This increases power dissipation, which decreases efficiency and exacerbates thermal concerns. This will limit how much the slew rate can be reduced. Another cost is the peak current of each cyle will be increased. It is because the slow edges reduce the on-time (ION_SR) and eventually the peak current (ISW_SR) will increase to deliver the same average current to the load on each cycle.

Figure 8-7 Slew Rate Control Scheme

The slew rate at different VIN is programmed by RSR. Higher RSR values configure SN6507 for slower slew rates across VCC levels while lower RSR values configure SN6507 for faster slew rates. The relationship between VCC and the slew rate for 12 V and 24 V cases are listed in Table 8-2 below. As the slew rate is independent of the switching frequency, care must be taken that at high frequencies, the slew rate should be fast enough to maximize the output power delivery to the load. If the SR pin is left floating, the slew rate will be set to the default value. An SR pin short to GND is read as a fault condition, and the device will stop switching.

Table 8-2 Slew Rate Control Look-up Table
VCC (V)RSR (kΩ)Typical SLEW RATE (V/μs)

5

4.8

337

5

Floating (Default)

263

5

15

224

5

21

198

124.8424
12Floating (Default)298
1215237
1221199
244.8583
24Floating (Default)369
2415273
2421218