SLLSEJ2G July 2015 – March 2020 SN65DP159 , SN75DP159
PRODUCTION DATA.
| ADDRESS | BIT | DEFAULT | DESCRIPTION | ACCESS | |
|---|---|---|---|---|---|
| 0Dh | 7:6 | 2’b00 | Reserved | RW | |
| 5:3 | 1’b000 | Data Lane EQ – Sets fixed EQ values | RW | ||
| HDMI1.4b[2]
000 – 0-dB 001 – 4.5-dB 010 – 6.5-dB 011 – 8.5-dB 100 – 10.5-dB 101 – 12-dB 110 – 14-dB 111 – 16.5-dB |
HDMI2.0[3]
000 – 0-dB 001 – 3-dB 010 – 5-dB 011 – 7.5-dB 100 – 9.5-dB 101 – 11-dB 110 – 13-dB 111 – 14.5-dB |
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| 2:1 | 1’b00 | Clock Lane EQ - Sets fixed EQ values | RW | ||
| HDMI1.4b[2]
00 – 0-dB 01 – 1.5-dB 10 – 3-dB 11 – RSVD |
HDMI2.0[3]
00 – 0-dB 01 – 1.5-dB 10 – 3-dB 11 – 4.5-dB |
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| 0 | 1’b0 |
0 – Clock VOD is half the set value when TMDS_CLOCK_RATIO_STATUS states in HDMI2.0 mode 1 – Disables TMDS_CLOCK_RATIO_STATUS control of the clock VOD so the output swing is full swing |
RW | ||