SLLSEJ2G July 2015 – March 2020 SN65DP159 , SN75DP159
PRODUCTION DATA.
Clock and data recovery circuits (CDR) are used to track, sample and retime the equalized data bit streams. The CDRs are designed with loop bandwidth to minimize the amount of jitter transfer from the video source to the TMDS outputs. Input jitter within the CDR’s PLL bandwidth, < 1-MHz, will be transferred to the TMDS outputs. Higher frequency jitter above the CDR loop bandwidth is attenuated, providing a jitter cleaning function to reduce the amount of high frequency jitter from the video source. The retimer is automatically activated at pixel clock above approximately 100-MHz when jitter cleaning is needed for robust operation. The retimer operates at about 1.0 to 6-Gbps DR supporting HDMI2.0[3]. At pixel clock frequency below about 100 MHz, the SNx5DP159 automatically bypasses the internal retimer and operates as a redriver. When the video source changes resolution, the internal retimer starts the acquisition process to determine the input clock frequency and acquire lock to the new data bit streams. During the clock frequency detection period and the retimer acquisition period (that last approximately 7-ms), the TMDS drivers can be kept active (default) or programmed to be disabled to avoid sending invalid clock or data to the downstream receiver.