SLLSEO9D March 2016 – October 2024 SN65DPHY440SS , SN75DPHY440SS
PRODUCTION DATA
The DPHY440 supports up to 4 DSI DPHY lanes and a clock lane. One of the four lanes is used for back channel communications between GPU and DSI panel. DPHY440’s lane 0 is the only lane that supports the back channel. For this reason, DPHY440 lane 0 must always be connected to lane 0 of GPU and panel.
Other combinations, like 1 and 3 lane, examples are not shown, but are fully supported by the DPHY440. For all DSI implementations, the polarity must be maintained between the DSI Source and DSI Sink. The DPHY440 does not support polarity inversion.