SLLSEO9D March   2016  – October 2024 SN65DPHY440SS , SN75DPHY440SS

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics, Power Supply
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 HS Receive Equalization
      2. 6.3.2 HS TX Edge Rate Control
      3. 6.3.3 TX Voltage Swing and Pre-Emphasis Control
      4. 6.3.4 Dynamic De-skew
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 LP Mode
      3. 6.4.3 ULPS Mode
      4. 6.4.4 HS Mode
    5. 6.5 Register Maps
      1. 6.5.1  BIT Access Tag Conventions
      2. 6.5.2  Standard CSR Registers (address = 0x000 - 0x07)
      3. 6.5.3  Standard CSR Register (address = 0x08)
      4. 6.5.4  Standard CSR Register (address = 0x09)
      5. 6.5.5  Standard CSR Register (address = 0x0A)
      6. 6.5.6  Standard CSR Register (address = 0x0B)
      7. 6.5.7  Standard CSR Register (address = 0x0D)
      8. 6.5.8  Standard CSR Register (address = 0x0E)
      9. 6.5.9  Standard CSR Register (address = 0x10) [reset = 0xFF]
      10. 6.5.10 Standard CSR Register (address = 0x11) [reset = 0xFF]
  8. 7 Application and Implementation
    1. 7.1 Application Information,
    2. 7.2 Typical Application, CSI-2 Implementations
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Reset Implementation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The DPHY440 is a 1-lane to 4-lane and clock MIPI® DPHY retimer that regenerates the DPHY signaling. The device complies with MIPI® DPHY 1.1 standard and can be used in either a MIPI® CSI-2 or MIPI® DSI application at datarates of up to 1.5Gbps.

The device compensates for PCB, connector, and cable related frequency loss and switching related loss to provide the optimum electrical performance from a CSI-2/DSI source to sink. The DPHY440 DPHY inputs feature configurable equalizers.

The output pins automatically compensate for uneven skew between clock and data lanes received on the inputs ports of the device. The DPHY440 output voltage swing and edge rate can be adjusted by changing the state of the VSADJ_CFG0 pin and ERC pin, respectively.

The DPHY440 is optimized for mobile applications, and contains activity detection circuitry on the DPHY Link interface that can transition into a lower power mode when in ULPS and LP states.

The SN65DPHY440SS is characterized for an industrial temperature range from –40°C to 85°C while SN75DPHY440SS is characterized for commercial temperature range from 0°C to 70°C.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
SN65DPHY440SS
SN75DPHY440SS		 (WQFN, 28) 5.5mm × 3.5mm
(1) For all available packages, see Section 10.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
SN65DPHY440SS SN75DPHY440SS Simplified SchematicSimplified Schematic
SN65DPHY440SS SN75DPHY440SS Typical ApplicationTypical Application