SLLSEO9D March 2016 – October 2024 SN65DPHY440SS , SN75DPHY440SS
PRODUCTION DATA
In some applications, the DPHY440 may be placed at a location in the system where the channel from DPHY440 DB[3:0]P/N interface to the DPHY Sink (CSI-2 or DSI) is extremely long and the DPHY Sink does not have enough receive equalization to compensate for the ISI loss. In this application, the system architect may want to use the DPHY440 TX pre-emphasis feature to compensate for the lack of equalization at the DPHY sink. The DPHY440 provides two levels of pre-emphasis: 0 dB, and 2.5 dB. The TX pre-emphasis settings is determined through the sampled sate of PRE_CFG[1:0] pins at the rising edge of RSTN. If necessary, the TX pre-emphasis settings can be adjusted by writing to the HSTX_PRE register through the local I2C interface.
This feature must only be used when the HS pre-emphasis bit (transition bit) is attenuated by the channel. Enabling pre-emphasis in a system that has little channel loss (transition bit is not attenuated) may result in negative impact to system performance.
VSADJ_CFG0 | PRE_CFG1 | HS TX VOD | HS TX PRE-EMPHASIS | DB[3:0] LP TX RISE/FALL TIME |
---|---|---|---|---|
≤ VIL | ≤ VIL | 200 mV | 0 dB | 18 ns |
VIM | ≤ VIL | 200 mV | 0 dB | 27 ns |
≥ VIH | ≤ VIL | 220 mV | 0 dB | 18 ns |
≤ VIL | VIM | 200 mV | 0 dB | 27 ns |
VIM | VIM | 200 mV | 0 dB | 21 ns |
≥ VIH | VIM | 220 mV | 0 dB | 21 ns |
≤ VIL | ≥ VIH | 220 mV | 2.5 dB | 27 ns |
VIM | ≥ VIH | 200 mV | 2.5 dB | 21 ns |
≥ VIH | ≥ VIH | 220 mV | 2.5 dB | 21 ns |