SLLSEO9D March   2016  – October 2024 SN65DPHY440SS , SN75DPHY440SS

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics, Power Supply
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 HS Receive Equalization
      2. 6.3.2 HS TX Edge Rate Control
      3. 6.3.3 TX Voltage Swing and Pre-Emphasis Control
      4. 6.3.4 Dynamic De-skew
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 LP Mode
      3. 6.4.3 ULPS Mode
      4. 6.4.4 HS Mode
    5. 6.5 Register Maps
      1. 6.5.1  BIT Access Tag Conventions
      2. 6.5.2  Standard CSR Registers (address = 0x000 - 0x07)
      3. 6.5.3  Standard CSR Register (address = 0x08)
      4. 6.5.4  Standard CSR Register (address = 0x09)
      5. 6.5.5  Standard CSR Register (address = 0x0A)
      6. 6.5.6  Standard CSR Register (address = 0x0B)
      7. 6.5.7  Standard CSR Register (address = 0x0D)
      8. 6.5.8  Standard CSR Register (address = 0x0E)
      9. 6.5.9  Standard CSR Register (address = 0x10) [reset = 0xFF]
      10. 6.5.10 Standard CSR Register (address = 0x11) [reset = 0xFF]
  8. 7 Application and Implementation
    1. 7.1 Application Information,
    2. 7.2 Typical Application, CSI-2 Implementations
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Reset Implementation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Timing Requirements

MIN NOM MAX UNIT
I2C (ERC (SDA), EQ (SCL))
tHD;STA Hold Time (repeated) START condition. After this period, the first clock pulse is generated 4 µs
tLOW Low period of SCL clock 4.7 µs
tHIGH High period of SCL clock 4 µs
tSU;STA Setup time for a repeated START condition 4.7 µs
tHD;DAT Data hold time 5 ns
tSU;DAT Data setup time 250 ns
tSU;STO Setup time for STOP condition 4 µs
tBUF Bus free time between a STOP and START condition 4.7 µs
fCLK I2C clock frequency 0 100 kHz
MIPI DPHY HS Interface
tHSPD Propagation delay from DA to DB. 4 + 12ns 4 + 40ns UI
tDBC_DCYCLE DAC to DBC output duty cycle distortion percentage 750 MHz clock with 50%-50% duty cycle at DAC input. –5 5 %
tSKEW-TX-1G Data to Clock variation from 0.5UI. Refer to Figure 5-2 Datarate ≤ 1 Gbps –0.1 0.1 UI
tSETUP-RX-1G Data to Clock setup time. Refer to Figure 5-2 Datarate ≤ 1 Gbps 0.1 UI
tHOLD-RX-1G Clock to data hold time. Refer to Figure 5-2 Datarate ≤ 1 Gbps 0.1 UI
tSKEW-TX-1P5G Data to Clock variation from 0.5UI. Refer to Figure 5-2 Datarate > 1 Gbps –0.15 0.15 UI
tSETUP-RX-1P5G Data to Clock setup time. Refer to Figure 5-2 Datarate > 1 Gbps 0.15 UI
tHOLD-RX-1P5G Clock to data hold time. Refer to Figure 5-2 Datarate > 1 Gbps 0.15 UI