SLLSEO9D March 2016 – October 2024 SN65DPHY440SS , SN75DPHY440SS
PRODUCTION DATA
The typical example describes how to configure the VSADJ, PRE, EQ and ERC configuration pins of the DPHY440 device based on the board trace length between the Source (Camera) and DPHY440 and the DPHY440 and Sink (APU). Actual configuration settings might differ due to additional factors such as board layout, and connectors used in the signal path.
Though the data rate in this example is 1 Gbps, device is placed near to the Sink, with a short output trace of 1 inch. Consequently, the ERC pin can be configured to have a rise/fall time of 250 ps for the edge. Further, due to the short output trace, the PRE pin must be configured to a setting of 0 dB and the VSADJ to be 200 mV. The Application Curve in Figure 7-6 shows the FR-4 loss characteristics of a 10 mil wide, 12 inch long trace. From this plot, the input signal trace suffers a loss of 1.5 dB at 500 MHz. Thus, the EQ setting can be either 0 dB or 2.5 dB. All the configuration settings and their corresponding inputs are tabulated in Table 7-2.
PIN | SETTING | INPUT VALUE |
---|---|---|
VSADJ | 200 mV | VIM |
PRE | 0 dB | VIM |
EQ | 0 dB or 2.5 dB | VIL or VIM |
ERC | 250 ps | VIH |
The configuration pins each have internal pull-up and pull-down resistors of 100 kΩ each. Thus, the recommendation is an external pull-up/pull-down resistors of about 10 kΩ each, to meet the requirement of the threshold levels for the VIL and VIH listed in the Electrical Characteristics table. The external resistors shown in Figure 7-2 should be populated to produce corresponding configuration settings, according to the list given in Table 7-3.
RESISTOR NAME | VALUE |
---|---|
R1 | Leave unpopulated |
R2 | Leave unpopulated |
R3 | Leave unpopulated |
R4 | Leave unpopulated |
R5 | Leave unpopulated |
R6 | 10 kΩ (EQ = 0 dB) or Leave unpopulated (EQ = 2.5 dB) |
R7 | 10 kΩ |
R8 | Leave unpopulated |