SLLSEO9D March   2016  – October 2024 SN65DPHY440SS , SN75DPHY440SS

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics, Power Supply
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 HS Receive Equalization
      2. 6.3.2 HS TX Edge Rate Control
      3. 6.3.3 TX Voltage Swing and Pre-Emphasis Control
      4. 6.3.4 Dynamic De-skew
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 LP Mode
      3. 6.4.3 ULPS Mode
      4. 6.4.4 HS Mode
    5. 6.5 Register Maps
      1. 6.5.1  BIT Access Tag Conventions
      2. 6.5.2  Standard CSR Registers (address = 0x000 - 0x07)
      3. 6.5.3  Standard CSR Register (address = 0x08)
      4. 6.5.4  Standard CSR Register (address = 0x09)
      5. 6.5.5  Standard CSR Register (address = 0x0A)
      6. 6.5.6  Standard CSR Register (address = 0x0B)
      7. 6.5.7  Standard CSR Register (address = 0x0D)
      8. 6.5.8  Standard CSR Register (address = 0x0E)
      9. 6.5.9  Standard CSR Register (address = 0x10) [reset = 0xFF]
      10. 6.5.10 Standard CSR Register (address = 0x11) [reset = 0xFF]
  8. 7 Application and Implementation
    1. 7.1 Application Information,
    2. 7.2 Typical Application, CSI-2 Implementations
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Reset Implementation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.1 Reset Implementation

The DPHY440 RSTN input gives control over the device reset and to place the device into low power mode. It is critical to reset the digital logic of the DPHY440 after the VCC supply is stable (that is, the power supply has reached the minimum recommended operating voltage). This is achieved by transitioning the RSTN input from a low level to a high level. A system may provide a control signal to the RSTN signal that transitions low to high after the power supply is (or supplies are) stable, or implement an external capacitor connected between RSTN and GND, to allow delaying the RSTN signal during power up. Both implementations are shown in Figure 7-3 and Figure 7-4.

SN65DPHY440SS SN75DPHY440SS External Capacitor Controlled RSTN Figure 7-3 External Capacitor Controlled RSTN
SN65DPHY440SS SN75DPHY440SS RSTN Input from Active Controller Figure 7-4 RSTN Input from Active Controller

When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of the VCC supply, where a slower ramp-up results in a larger value external capacitor.

Refer to the latest reference schematic for the DPHY440 device and/or consider approximately 200-nF capacitor as a reasonable first estimate for the size of the external capacitor.

When implementing an RSTN input from an active controller, it is recommended to use an open drain driver if the RSTN input is driven. This protects the RSTN input from damage of an input voltage greater than VCC.

SN65DPHY440SS SN75DPHY440SS Power-Up Timing Requirements Figure 7-5 Power-Up Timing Requirements
Table 7-4 Timing Requirements
DESCRIPTION(1) MIN MAX
tD1 VCC stable before deassertion of RSTN. 100 µs
tsu2 Setup of VSADJ_CFG0, PRE_CFG1, EQ and ERC pin before deassertion of RSTN. 0
th2 Hold of VSADJ_CFG0, PRE_CFG1, EQ and ERC pin after deassertion of RSTN. 250 µs
tVCC_RAMP VCC supply ramp requirements 0.2 ms 100 ms
(1) Unused DAxP/N pins shall be tied to GND.