SLLSEO9D March 2016 – October 2024 SN65DPHY440SS , SN75DPHY440SS
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Standard IO (RSTN, ERC, EQ, CFG[1:0]) | ||||||
| VIL | Low-level control signal input voltage | 0.2 x VCC | V | |||
| VIM | Mid-level control signal input voltage | VCC / 2 | V | |||
| VIH | High-level control signal input voltage | 0.8 x VCC | V | |||
| VF | Floating Voltage | VIN = High Impedance | VCC / 2 | V | ||
| VOL | Low level output voltage (open-drain). ERC (SDA) only | At IOL max. | 0.2 x VCC | V | ||
| IOL | Low Level Output Current | 3 | mA | |||
| IIH | High level input current | ±36 | µA | |||
| IIL | Low level input current | ±36 | µA | |||
| RPU | Internal pull-up resistance | 100 | kΩ | |||
| RPD | Internal pull-down resistance | 100 | kΩ | |||
| R(RSTN) | RSTN control input pullup resistor | 300 | kΩ | |||
| MIPI Input Leakage (DA1P/N, DA2P/N, DA3P/N, DACP/N) | ||||||
| Ilkg | Input failsafe leakage current | VCC = 0 V; VDD = 0 V; MIPI DPHY pulled up to 1.35 V | –65 | 65 | µAV | |
| MIPI DPHY HS RECIEVER INTERFACE (DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N) | ||||||
| V(CM-RX_DC) | Differential Input Common-mode voltage HS Receive mode | V(CM-RX) = (VA x P + VA x N)/2 | 70 | 330 | mV | |
| | VID | | HS Receiver input differential voltage | | VID | = |VA x P – VA x N| | 70 | mV | ||
| VIH(HS) | Single-ended input high voltage | 460 | mV | |||
| VIL(HS) | Single-ended input low voltage | –40 | mV | |||
| R(DIFF-HS) | Differential input impedance | 80 | 100 | 125 | Ω | |
| V(RXEQ0) | RX EQ gain when EQ/SCL pin ≤ VIL | 0 | dB | |||
| V(RXEQ1) | RX EQ gain when EQ/SCL pin = VIM | At 750 MHz | 2.5 | dB | ||
| V(RXEQ2) | RX EQ gain when EQ/SCL pin ≥ VIH | At 750 MHz | 5 | dB | ||
| MIPI DPHY LP Receiver Interface (DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N, DB0P/N) | ||||||
| V(LPIH) | LP Logic 1 Input Voltage | 880 | mV | |||
| V(LPIL) | LP Logic 0 Input voltage | 550 | mV | |||
| V(HYST) | LP Input Hysteresis | 25 | mV | |||
| MIPI DPHY HS Transmitter Interface (DB0P/N, DB1P/N, DB2P/N, DB3P/N, DBCP/N) | ||||||
| V(CMTX) | HS Transmit static common-mode voltage | V(CMTX) = (V(BP) + V(BN)) / 2 | 150 | 200 | 300 | mV |
| |∆V(CMTX) (1,0)| | VCMTX mismatch when output is Differential-1 or differential-0. | ∆V(CMTX) (1,0) = (V(CMTX) (1) – V(CMTX) (0)) /2 | 5 | mV | ||
| |VOD(VD0)| | HS Transmit differential voltage for CFG0 = 2’b00 with TX pre-emphasis disabled or for non-transition bit when TX pre-emphasis is enabled. | |VOD| = |V(DP) - V(DN)| | 140 | 180 | 220 | mV |
| |VOD(VD1)| | HS Transmit differential voltage for CFG0 = VIM with TX pre-emphasis disabled or for non-transition bit when TX pre-emphasis is enabled. | |VOD| = |V(DP) - V(DN)| CFG0 = VIM | 160 | 200 | 250 | mV |
| |VOD(VD2)| | HS Transmit differential voltage for CFG0 = VIH with TX pre-emphasis disabled or for non-transition bit when pre-emphasis is enabled.. | |VOD| = |V(DP) - V(DN)| CFG0 ≥ VIH | 170 | 220 | 270 | mV |
| |∆VOD| | VOD mismatch when output is differential-1 or differential-0. | ∆VOD = |∆VO(D1)| - |∆VO(D0)| | 14 | mV | ||
| VOH(HS) | HS Output high voltage for non-transition bit. | CFG0 ≥ VIH HS Pre = 2.5 dB | 430 | mV | ||
| V(PRE1) | Pre-emphasis Level for HSTX_PRE = 2’b00.. Refer to Figure 5-3 | PRE = 20 x LOG (VOD(TBx) / VOD(VDX)) | 1.5 | dB | ||
| V(PRE2) | Pre-emphasis level for HSTX_PRE = 2’b1X. Refer to Figure 5-3 | PRE = 20 x LOG (VOD(TBx) / VOD(VDX)) | 2.5 | dB | ||
| MIPI DPHY LP Transmitter Interface (DB0P/N, DB1P/N, DB2P/N, DB3P/N, DBCP/N, DA0P/N) | ||||||
| V(LPOH) | LP Output High Level | 1.1 | 1.2 | 1.3 | V | |
| V(LPOL) | LP Output Low Level | –50 | 50 | mV | ||
| VIH(CD) | LP Logic 1 contention threshold | 450 | mV | |||
| VIL(CD) | LP Logc 0 contention threshold | 200 | mV | |||
| ZO(LP) | Output Impedance of LP transmitter | 110 | Ω | |||