SLLSEW7A December   2016  – June 2018 SN65DSI83-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     SN65DSI83-Q1 Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clock Configurations and Multipliers
      2. 8.3.2 ULPS
      3. 8.3.3 LVDS Pattern Generation
      4. 8.3.4 Reset Implementation
      5. 8.3.5 Initialization Sequence
      6. 8.3.6 LVDS Output Formats
      7. 8.3.7 DSI Lane Merging
      8. 8.3.8 DSI Pixel Stream Packets
      9. 8.3.9 DSI Video Transmission Specifications
    4. 8.4 Programming
      1. 8.4.1 Local I2C Interface Overview
    5. 8.5 Register Maps
      1. 8.5.1 Control and Status Registers Overview
        1. 8.5.1.1 CSR Bit Field Definitions – ID Registers
          1. 8.5.1.1.1 Registers 0x00 – 0x08
            1. Table 4. Registers 0x00 – 0x08 Field Descriptions
        2. 8.5.1.2 CSR Bit Field Definitions – Reset and Clock Registers
          1. 8.5.1.2.1 Register 0x09
            1. Table 5. Register 0x09 Field Descriptions
          2. 8.5.1.2.2 Register 0x0A
            1. Table 6. Register 0x0A Field Descriptions
          3. 8.5.1.2.3 Register 0x0B
            1. Table 7. Register 0x0B Field Descriptions
          4. 8.5.1.2.4 Register 0x0D
            1. Table 8. Register 0x0D Field Descriptions
        3. 8.5.1.3 CSR Bit Field Definitions – DSI Registers
          1. 8.5.1.3.1 Register 0x10
            1. Table 9. Register 0x10 Field Descriptions
          2. 8.5.1.3.2 Register 0x11
            1. Table 10. Register 0x11 Field Descriptions
          3. 8.5.1.3.3 Register 0x12
            1. Table 11. Register 0x12 Field Descriptions
        4. 8.5.1.4 CSR Bit Field Definitions – LVDS Registers
          1. 8.5.1.4.1 Register 0x18
            1. Table 12. Register 0x18 Field Descriptions
          2. 8.5.1.4.2 Register 0x19
            1. Table 13. Register 0x19 Field Descriptions
          3. 8.5.1.4.3 Register 0x1A
            1. Table 14. Register 0x1A Field Descriptions
          4. 8.5.1.4.4 Register 0x1B
            1. Table 15. Register 0x1B Field Descriptions
        5. 8.5.1.5 CSR Bit Field Definitions – Video Registers
          1. 8.5.1.5.1  Register 0x20
            1. Table 16. Register 0x20 Field Descriptions
          2. 8.5.1.5.2  Register 0x21
            1. Table 17. Register 0x21 Field Descriptions
          3. 8.5.1.5.3  Register 0x24
            1. Table 18. Register 0x24 Field Descriptions
          4. 8.5.1.5.4  Register 0x25
            1. Table 19. Register 0x25 Field Descriptions
          5. 8.5.1.5.5  Register 0x28
            1. Table 20. Register 0x28 Field Descriptions
          6. 8.5.1.5.6  Register 0x29
            1. Table 21. Register 0x29 Field Descriptions
          7. 8.5.1.5.7  Register 0x2C
            1. Table 22. Register 0x2C Field Descriptions
          8. 8.5.1.5.8  Register 0x2D
            1. Table 23. Register 0x2D Field Descriptions
          9. 8.5.1.5.9  Register 0x30
            1. Table 24. Register 0x30 Field Descriptions
          10. 8.5.1.5.10 Register 0x31
            1. Table 25. Register 0x31 Field Descriptions
          11. 8.5.1.5.11 Register 0x34
            1. Table 26. Register 0x34 Field Descriptions
          12. 8.5.1.5.12 Register 0x36
            1. Table 27. Register 0x36 Field Descriptions
          13. 8.5.1.5.13 Register 0x38
            1. Table 28. Register 0x38 Field Descriptions
          14. 8.5.1.5.14 Register 0x3A
            1. Table 29. Register 0x3A Field Descriptions
          15. 8.5.1.5.15 Register 0x3C
            1. Table 30. Register 0x3C Field Descriptions
        6. 8.5.1.6 CSR Bit Field Definitions – IRQ Registers
          1. 8.5.1.6.1 Register 0xE0
            1. Table 31. Register 0xE0 Field Descriptions
          2. 8.5.1.6.2 Register 0xE1
            1. Table 32. Register 0xE1 Field Descriptions
          3. 8.5.1.6.3 Register 0xE5
            1. Table 33. Register 0xE5 Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Video STOP and Restart Sequence
      2. 9.1.2 Reverse LVDS Pin Order Option
      3. 9.1.3 IRQ Usage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Example Script
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCORE Power Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Package Specific
      2. 11.1.2 Differential Pairs
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.1 Local I2C Interface Overview

The SN65DSI83-Q1 device local I2C interface is enabled when EN is input high, access to the CSR registers is supported during ULPS. The SCL and SDA pins are used for I2C clock and I2C data respectively. The SN65DSI83-Q1 device I2C interface conforms to the 2-wire serial interface defined by the I2C Bus Specification, Version 2.1 (January 2000) and supports fast mode transfers up to 400 kbps.

The device address byte is the first byte received following the start condition from the master device. The 7-bit device address for SN65DSI83-Q1 device is factory preset to 010110X with the least significant bit being determined by the ADDR control input. Table 3 clarifies the SN65DSI83-Q1 device target address.

Table 3. SN65DSI83-Q1 I2C Target Address Description (1)(2)

BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (W/R)
0 1 0 1 1 0 ADDR 0/1
(1) When ADDR = 1, Address cycle is 0×5A (write) and 0×5B (read)
(2) When ADDR = 0, Address cycle is 0×58 (write) and 0×59 (read)

The following procedure is followed to write to the SN65DSI83-Q1 device I2C registers:

  1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI83-Q1 device 7-bit address and a zero-value W/R bit to indicate a write cycle.
  2. The SN65DSI83-Q1 device acknowledges the address cycle.
  3. The master presents the subaddress (I2C register within SN65DSI83-Q1 device) to be written, consisting of one byte of data, MSB-first.
  4. The SN65DSI83-Q1 device acknowledges the subaddress cycle.
  5. The master presents the first byte of data to be written to the I2C register.
  6. The SN65DSI83-Q1 device acknowledges the byte transfer.
  7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the SN65DSI83-Q1 device.
  8. The master terminates the write operation by generating a stop condition (P).

The following procedure is followed to read the SN65DSI83-Q1 I2C registers:

  1. The master initiates a read operation by generating a start condition (S), followed by the SN65DSI83-Q1 device 7-bit address and a one-value W/R bit to indicate a read cycle.
  2. The SN65DSI83-Q1 device acknowledges the address cycle.
  3. The SN65DSI83-Q1 device transmits the contents of the memory registers MSB-first starting at register 00h. If a write to the SN65DSI83-Q1 I2C register occurred prior to the read, then the SN65DSI83-Q1 device starts at the subaddress specified in the write.
  4. The SN65DSI83-Q1 device waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
  5. If an ACK is received, the SN65DSI83-Q1 device transmits the next byte of data.
  6. The master terminates the read operation by generating a stop condition (P).

The following procedure is followed for setting a starting subaddress for I2C reads:

  1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI83-Q1 device 7-bit address and a zero-value W/R bit to indicate a write cycle.
  2. The SN65DSI83-Q1 device acknowledges the address cycle.
  3. The master presents the subaddress (I2C register within the SN65DSI83-Q1 device) to be written, consisting of one byte of data, MSB first.
  4. The SN65DSI83-Q1 device acknowledges the subaddress cycle.
  5. The master terminates the write operation by generating a stop condition (P).