SLLSEW7A December 2016 – June 2018 SN65DSI83-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHA_DSI_CLK_RANGE | |||||||
R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | CHA_DSI_CLK_RANGE | R/W | 0 | This field specifies the DSI Clock frequency range in 5 MHz increments for the DSI Channel A Clock
0x00 through 0x07 – Reserved 0x08 – 40 ≤ frequency < 45 MHz 0x09 – 45 ≤ frequency < 50 MHz ... 0x63 – 495 ≤ frequency < 500 MHz 0x64 – 500 MHz 0x65 through 0xFF – Reserved |