SLLSEW9A
December 2016 – June 2018
SN65DSI84-Q1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
3.1
Typical Application
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Clock Configurations and Multipliers
8.3.2
ULPS
8.3.3
LVDS Pattern Generation
8.4
Device Functional Modes
8.4.1
Reset Implementation
8.4.2
Initialization Sequence
8.4.3
LVDS Output Formats
8.4.4
DSI Lane Merging
8.4.5
DSI Pixel Stream Packets
8.4.6
DSI Video Transmission Specifications
8.4.7
Operating Modes
8.5
Programming
8.5.1
Local I2C Interface Overview
8.6
Register Maps
8.6.1
Control and Status Registers Overview
8.6.1.1
CSR Bit Field Definitions – ID Registers
8.6.1.1.1
Registers 0x00 – 0x08
Table 5.
Registers 0x00 – 0x08 Field Descriptions
8.6.1.2
CSR Bit Field Definitions – Reset and Clock Registers
8.6.1.2.1
Register 0x09
Table 6.
Register 0x09 Field Descriptions
8.6.1.2.2
Register 0x0A
Table 7.
Register 0x0A Field Descriptions
8.6.1.2.3
Register 0x0B
Table 8.
Register 0x0B Field Descriptions
8.6.1.2.4
Register 0x0D
Table 9.
Register 0x0D Field Descriptions
8.6.1.3
CSR Bit Field Definitions – DSI Registers
8.6.1.3.1
Register 0x10
Table 10.
Register 0x10 Field Descriptions
8.6.1.3.2
Register 0x11
Table 11.
Register 0x11 Field Descriptions
8.6.1.3.3
Register 0x12
Table 12.
Register 0x12 Field Descriptions
8.6.1.4
CSR Bit Field Definitions – LVDS Registers
8.6.1.4.1
Register 0x18
Table 13.
Register 0x18 Field Descriptions
8.6.1.4.2
Register 0x19
Table 14.
Register 0x19 Field Descriptions
8.6.1.4.3
Register 0x1A
Table 15.
Register 0x1A Field Descriptions
8.6.1.4.4
Register 0x1B
Table 16.
Register 0x1B Field Descriptions
8.6.1.5
CSR Bit Field Definitions – Video Registers
8.6.1.5.1
Register 0x20
Table 17.
Register 0x20 Field Descriptions
8.6.1.5.2
Register 0x21
Table 18.
Register 0x21 Field Descriptions
8.6.1.5.3
Register 0x24
Table 19.
Register 0x24 Field Descriptions
8.6.1.5.4
Register 0x25
Table 20.
Register 0x25 Field Descriptions
8.6.1.5.5
Register 0x28
Table 21.
Register 0x28 Field Descriptions
8.6.1.5.6
Register 0x29
Table 22.
Register 0x29 Field Descriptions
8.6.1.5.7
Register 0x2C
Table 23.
Register 0x2C Field Descriptions
8.6.1.5.8
Register 0x2D
Table 24.
Register 0x2D Field Descriptions
8.6.1.5.9
Register 0x30
Table 25.
Register 0x30 Field Descriptions
8.6.1.5.10
Register 0x31
Table 26.
Register 0x31 Field Descriptions
8.6.1.5.11
Register 0x34
Table 27.
Register 0x34 Field Descriptions
8.6.1.5.12
Register 0x36
Table 28.
Register 0x36 Field Descriptions
8.6.1.5.13
Register 0x38
Table 29.
Register 0x38 Field Descriptions
8.6.1.5.14
Register 0x3A
Table 30.
Register 0x3A Field Descriptions
8.6.1.5.15
Register 0x3C
Table 31.
Register 0x3C Field Descriptions
8.6.1.6
CSR Bit Field Definitions – IRQ Registers
8.6.1.6.1
Register 0xE0
Table 32.
Register 0xE0 Field Descriptions
8.6.1.6.2
Register 0xE1
Table 33.
Register 0xE1 Field Descriptions
8.6.1.6.3
Register 0xE5
Table 34.
Register 0xE5 Field Descriptions
9
Application and Implementation
9.1
Application Information
9.1.1
Video Stop and Restart Sequence
9.1.2
Reverse LVDS Pin Order Option
9.1.3
IRQ Usage
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Example Script
9.2.3
Application Curve
10
Power Supply Recommendations
10.1
VCC Power Supply
10.2
VCORE Power Supply
11
Layout
11.1
Layout Guidelines
11.1.1
Package Specific
11.1.2
Differential Pairs
11.1.3
Ground
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Community Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PAP|64
MPQF071C
Thermal pad, mechanical data (Package|Pins)
PAP|64
PPTD318A
Orderable Information
sllsew9a_oa
sllsew9a_pm
8.6.1.5
CSR Bit Field Definitions – Video Registers