SLLSEW9A December   2016  – June 2018 SN65DSI84-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clock Configurations and Multipliers
      2. 8.3.2 ULPS
      3. 8.3.3 LVDS Pattern Generation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset Implementation
      2. 8.4.2 Initialization Sequence
      3. 8.4.3 LVDS Output Formats
      4. 8.4.4 DSI Lane Merging
      5. 8.4.5 DSI Pixel Stream Packets
      6. 8.4.6 DSI Video Transmission Specifications
      7. 8.4.7 Operating Modes
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface Overview
    6. 8.6 Register Maps
      1. 8.6.1 Control and Status Registers Overview
        1. 8.6.1.1 CSR Bit Field Definitions – ID Registers
          1. 8.6.1.1.1 Registers 0x00 – 0x08
            1. Table 5. Registers 0x00 – 0x08 Field Descriptions
        2. 8.6.1.2 CSR Bit Field Definitions – Reset and Clock Registers
          1. 8.6.1.2.1 Register 0x09
            1. Table 6. Register 0x09 Field Descriptions
          2. 8.6.1.2.2 Register 0x0A
            1. Table 7. Register 0x0A Field Descriptions
          3. 8.6.1.2.3 Register 0x0B
            1. Table 8. Register 0x0B Field Descriptions
          4. 8.6.1.2.4 Register 0x0D
            1. Table 9. Register 0x0D Field Descriptions
        3. 8.6.1.3 CSR Bit Field Definitions – DSI Registers
          1. 8.6.1.3.1 Register 0x10
            1. Table 10. Register 0x10 Field Descriptions
          2. 8.6.1.3.2 Register 0x11
            1. Table 11. Register 0x11 Field Descriptions
          3. 8.6.1.3.3 Register 0x12
            1. Table 12. Register 0x12 Field Descriptions
        4. 8.6.1.4 CSR Bit Field Definitions – LVDS Registers
          1. 8.6.1.4.1 Register 0x18
            1. Table 13. Register 0x18 Field Descriptions
          2. 8.6.1.4.2 Register 0x19
            1. Table 14. Register 0x19 Field Descriptions
          3. 8.6.1.4.3 Register 0x1A
            1. Table 15. Register 0x1A Field Descriptions
          4. 8.6.1.4.4 Register 0x1B
            1. Table 16. Register 0x1B Field Descriptions
        5. 8.6.1.5 CSR Bit Field Definitions – Video Registers
          1. 8.6.1.5.1  Register 0x20
            1. Table 17. Register 0x20 Field Descriptions
          2. 8.6.1.5.2  Register 0x21
            1. Table 18. Register 0x21 Field Descriptions
          3. 8.6.1.5.3  Register 0x24
            1. Table 19. Register 0x24 Field Descriptions
          4. 8.6.1.5.4  Register 0x25
            1. Table 20. Register 0x25 Field Descriptions
          5. 8.6.1.5.5  Register 0x28
            1. Table 21. Register 0x28 Field Descriptions
          6. 8.6.1.5.6  Register 0x29
            1. Table 22. Register 0x29 Field Descriptions
          7. 8.6.1.5.7  Register 0x2C
            1. Table 23. Register 0x2C Field Descriptions
          8. 8.6.1.5.8  Register 0x2D
            1. Table 24. Register 0x2D Field Descriptions
          9. 8.6.1.5.9  Register 0x30
            1. Table 25. Register 0x30 Field Descriptions
          10. 8.6.1.5.10 Register 0x31
            1. Table 26. Register 0x31 Field Descriptions
          11. 8.6.1.5.11 Register 0x34
            1. Table 27. Register 0x34 Field Descriptions
          12. 8.6.1.5.12 Register 0x36
            1. Table 28. Register 0x36 Field Descriptions
          13. 8.6.1.5.13 Register 0x38
            1. Table 29. Register 0x38 Field Descriptions
          14. 8.6.1.5.14 Register 0x3A
            1. Table 30. Register 0x3A Field Descriptions
          15. 8.6.1.5.15 Register 0x3C
            1. Table 31. Register 0x3C Field Descriptions
        6. 8.6.1.6 CSR Bit Field Definitions – IRQ Registers
          1. 8.6.1.6.1 Register 0xE0
            1. Table 32. Register 0xE0 Field Descriptions
          2. 8.6.1.6.2 Register 0xE1
            1. Table 33. Register 0xE1 Field Descriptions
          3. 8.6.1.6.3 Register 0xE5
            1. Table 34. Register 0xE5 Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Video Stop and Restart Sequence
      2. 9.1.2 Reverse LVDS Pin Order Option
      3. 9.1.3 IRQ Usage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Example Script
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCORE Power Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Package Specific
      2. 11.1.2 Differential Pairs
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.1 Example Script

This example configures the SN65DSI84-Q1 for the following configuration:

<aardvark> <configure i2c="1" spi="1" gpio="0" tpower="1" pullups="1"/> <i2c_bitrate khz="100"/> =====SOFTRESET======= <i2c_write addr="0x2D" count="1" radix="16"glt;09 01</i2c_writeglt; <sleep ms="10"/> ======ADDR 0D======= ======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured====== <i2c_write addr="0x2D" count="1" radix="16"glt;0D 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 0A======= ======HS_CLK_SRC bit0=== ======LVDS_CLK_Range bit 3:1====== <i2c_write addr="0x2D" count="1" radix="16"glt;0A 05</i2c_writeglt; <sleep ms="10"/> ======ADDR 0B======= ======DSI_CLK_DIVIDER bit7:3===== ======RefCLK multiplier(bit1:0)====== ======00 - LVDSclk=source clk, 01 - x2, 10 -x3, 11 - x4====== <i2c_write addr="0x2D" count="1" radix="16"glt;0B 28</i2c_writeglt; <sleep ms="10"/> ======ADDR 10======= ======DSI Ch Confg Left_Right Pixels(bit7 - 0 for A ODD, B EVEN, 1 for the other config)====== ======DSI Ch Mode(bit6:5) 00 - Dual, 01 - single, 10 - two single ======= ======CHA_DSI_Lanes(bit4:3), CHB_DSI_Lanes(bit2:1), 00 - 4, 01 - 3, 10 - 2, 11 - 1 ======SOT_ERR_TOL_DIS(bit0)======= <i2c_write addr="0x2D" count="1" radix="16"glt;10 26</i2c_writeglt; <sleep ms="10"/> ======ADDR 12======= <i2c_write addr="0x2D" count="1" radix="16"glt;12 62</i2c_writeglt; <sleep ms="10"/> ======ADDR 18======= ======bit7: DE_Pol, bit6:HS_Pol, bit5:VS_Pol, bit4: LVDS Link Cfg, bit3:CHA 24bpp, bit2: CHB 24bpp, bit1: CHA 24bpp fmt1, bit0: CHB 24bpp fmt1====== <i2c_write addr="0x2D" count="1" radix="16"glt;18 63</i2c_writeglt; <sleep ms="10"/> ======ADDR 19======= <i2c_write addr="0x2D" count="1" radix="16"glt;19 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 1A======= <i2c_write addr="0x2D" count="1" radix="16"glt;1A 03</i2c_writeglt; <sleep ms="10"/> ======ADDR 20======= ======CHA_LINE_LENGTH_LOW======== <i2c_write addr="0x2D" count="1" radix="16"glt;20 80</i2c_writeglt; <sleep ms="10"/> ======ADDR 21======= ======CHA_LINE_LENGTH_HIGH======== <i2c_write addr="0x2D" count="1" radix="16"glt;21 07</i2c_writeglt; <sleep ms="10"/> ======ADDR 22======= ======CHB_LINE_LENGTH_LOW======== <i2c_write addr="0x2D" count="1" radix="16"glt;22 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 23======= ======CHB_LINE_LENGTH_HIGH======== <i2c_write addr="0x2D" count="1" radix="16"glt;23 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 24======= ======CHA_VERTICAL_DISPLAY_SIZE_LOW======== <i2c_write addr="0x2D" count="1" radix="16"glt;24 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 25======= ======CHA_VERTICAL_DISPLAY_SIZE_HIGH======== <i2c_write addr="0x2D" count="1" radix="16"glt;25 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 26======= ======CHB_VERTICAL_DISPLAY_SIZE_LOW======== <i2c_write addr="0x2D" count="1" radix="16"glt;26 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 27======= ======CHB_VERTICAL_DISPLAY_SIZE_HIGH======== <i2c_write addr="0x2D" count="1" radix="16"glt;27 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 28======= ======CHA_SYNC_DELAY_LOW======== <i2c_write addr="0x2D" count="1" radix="16"glt;28 20</i2c_writeglt; <sleep ms="10"/> ======ADDR 29======= ======CHA_SYNC_DELAY_HIGH======== <i2c_write addr="0x2D" count="1" radix="16"glt;29 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 2A======= ======CHB_SYNC_DELAY_LOW======== <i2c_write addr="0x2D" count="1" radix="16"glt;2A 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 2B======= ======CHB_SYNC_DELAY_HIGH======== <i2c_write addr="0x2D" count="1" radix="16"glt;2B 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 2C======= ======CHA_HSYNC_PULSE_WIDTH_LOW======== <i2c_write addr="0x2D" count="1" radix="16"glt;2C 32</i2c_writeglt; <sleep ms="10"/> ======ADDR 2D======= ======CHA_HSYNC_PULSE_WIDTH_HIGH======== <i2c_write addr="0x2D" count="1" radix="16"glt;2D 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 2E======= ======CHB_HSYNC_PULSE_WIDTH_LOW======== <i2c_write addr="0x2D" count="1" radix="16"glt;2E 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 2F======= ======CHB_HSYNC_PULSE_WIDTH_HIGH======== <i2c_write addr="0x2D" count="1" radix="16"glt;2F 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 30======= ======CHA_VSYNC_PULSE_WIDTH_LOW======== <i2c_write addr="0x2D" count="1" radix="16"glt;30 05</i2c_writeglt; <sleep ms="10"/> ======ADDR 31======= ======CHA_VSYNC_PULSE_WIDTH_HIGH======== <i2c_write addr="0x2D" count="1" radix="16"glt;31 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 32======= ======CHB_VSYNC_PULSE_WIDTH_LOW======== <i2c_write addr="0x2D" count="1" radix="16"glt;32 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 33======= ======CHB_VSYNC_PULSE_WIDTH_HIGH======== <i2c_write addr="0x2D" count="1" radix="16"glt;33 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 34======= ======CHA_HOR_BACK_PORCH======== <i2c_write addr="0x2D" count="1" radix="16"glt;34 2C</i2c_writeglt; <sleep ms="10"/> ======ADDR 35======= ======CHB_HOR_BACK_PORCH======== <i2c_write addr="0x2D" count="1" radix="16"glt;35 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 36======= ======CHA_VER_BACK_PORCH======== <i2c_write addr="0x2D" count="1" radix="16"glt;36 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 37======= ======CHB_VER_BACK_PORCH======== <i2c_write addr="0x2D" count="1" radix="16"glt;37 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 38======= ======CHA_HOR_FRONT_PORCH======== <i2c_write addr="0x2D" count="1" radix="16"glt;38 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 39======= ======CHB_HOR_FRONT_PORCH======== <i2c_write addr="0x2D" count="1" radix="16"glt;39 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 3A======= ======CHA_VER_FRONT_PORCH======== <i2c_write addr="0x2D" count="1" radix="16"glt;3A 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 3B======= ======CHB_VER_FRONT_PORCH======== <i2c_write addr="0x2D" count="1" radix="16"glt;3B 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 3C======= ======CHA/CHB TEST PATTERN(bit4 CHA, bit0 CHB)======== <i2c_write addr="0x2D" count="1" radix="16"glt;3C 00</i2c_writeglt; <sleep ms="10"/> ======ADDR 0D======= ======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured====== <i2c_write addr="0x2D" count="1" radix="16"glt;0D 01</i2c_writeglt; <sleep ms="10"/> =====SOFTRESET======= <i2c_write addr="0x2D" count="1" radix="16"glt;09 00</i2c_writeglt; <sleep ms="10"/> ======write====== <i2c_write addr="0x2D" count="196" radix="16"glt;00</i2c_writeglt; <sleep ms="10"/> ======Read====== <i2c_read addr="0x2D" count="256" radix="16"glt;00</i2c_readglt; <sleep ms="10"/> </aardvark>