SLLSEW9A December 2016 – June 2018 SN65DSI84-Q1
PRODUCTION DATA.
The SN65DSI84-Q1 supports the MIPI defined ultra-low power state (ULPS). While the device is in the ULPS, the CSR registers are accessible via I2C interface. ULPS sequence should be issued to all active DSI CLK and/or DSI data lanes of the enabled DSI Channels for the SN65DSI84-Q1 enter the ULPS. The Following sequence should be followed to enter and exit the ULPS.