SN65DSIx6-Q1 MIPI® DSI to eDP™ Bridge
- SLLSEJ5A July 2014 – December 2015 SN65DSI86-Q1
  
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DATA SHEET

SN65DSIx6-Q1 MIPI® DSI to eDP™ Bridge

1 Features

Embedded DisplayPort™ (eDP™) 1.4 Compliant Supporting 1, 2, or 4 Lanes at 1.62 Gbps (RBR), 2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2).
Implements MIPI® D-PHY Version 1.1 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
Dual-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1.5 Gbps Per Lane
Supports 18 bpp and 24 bpp DSI Video Packets With RGB666 and RGB888 Formats
Suitable for 60 fps 4K 4096 × 2304 Resolution at 18 bpp Color, and WUXGA 1920 × 1200 Resolution with 3D Graphics at 60 fps (120 fps Equivalent)
MIPI Front-End Configurable for Single-Channel or Dual-Channel DSI Configuration
Supports Dual-Channel DSI Odd, Even and Left, Right Operating Modes
1.2-V Main VCC Power Supply and 1.8-V Supply for Digital I/Os
Low-Power Features Include Panel Refresh and MIPI Ultralow Power State (ULPS) Support
DisplayPort Lane Polarity and Assignment Configurable.
Supports 12-MHz, 19.2-MHz, 26-MHz, 27-MHz, and 38.4-MHz Frequencies Through External Reference Clock (REFCLK)
ESD Rating ±2 kV (HBM)
Packaged in 64-Terminal HTQFP (PAP)
Temperature Range: –40°C to +85°C

2 Applications

Tablet PCs, Notebook PCs, Netbooks
Mobile Internet Devices/Automotive Infotainment

3 Description

The SN65DSI86-Q1 DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.

The SN65DSI86-Q1 is well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
SN65DSI86-Q1	HTQFP (64)	10 mm x 10 mm

For all available packages, see the package option addendum at the end of the datasheet.

4 Revision History

Changes from * Revision (July 2014) to A Revision

Changed Description for ADDRESS 0x5A BIT(S) 1:0 from 'Reserved' to 'ASSR_CONTROL' with Bit assignments of 00, 01, 10, and 11 in Table 23.Go
Added Table 33 in Standard CFR Registers Go

5 Description (continued)

Designed with industry compliant interface technology, the is compatible with a wide range of microprocessors, and is designed with a range of power management features, including panel refresh support, and the MIPI defined ultralow power state (ULPS) support.

The SN65DSI86 Q1 is implemented in a 10-mm × 10-mm HTQFP at 0.5-mm pitch package, and operates across a temperature range from –40°C to +85°C.

In the rest of this document, the SN65DSI86-Q1 is referred to as SN65DSIx6 or DSIx6.

6 Pin Configuration and Functions

PAP Package

64-Pin HTQFP

Top View

See Layout Guidelines for additional information.

Pin Functions

PIN		TYPE	DESCRIPTION
NAME	NO.	TYPE	DESCRIPTION
DA0P	19	I	MIPI D-PHY Channel A Data Lane 0; data rate up to 1.5 Gbps.
DA0N	20	I	MIPI D-PHY Channel A Data Lane 0; data rate up to 1.5 Gbps.
DA1P	21	I	MIPI D-PHY Channel A Data Lane 1; data rate up to 1.5 Gbps.
DA1N	22	I	MIPI D-PHY Channel A Data Lane 1; data rate up to 1.5 Gbps.
DACP	24	I	MIPI D-PHY Channel A Clock Lane; operates up to 750MHz. Under proper conditions, this clock can be used instead of REFCLK to feed DP_PLL
DACN	25	I
DA2P	27	I	MIPI D-PHY Channel A Data Lane 2; data rate up to 1.5 Gbps.
DA2N	28	I	MIPI D-PHY Channel A Data Lane 2; data rate up to 1.5 Gbps.
DA3P	29	I	MIPI D-PHY Channel A Data Lane 3; data rate up to 1.5 Gbps.
DA3N	30	I	MIPI D-PHY Channel A Data Lane 3; data rate up to 1.5 Gbps.
DB0P	4	I	MIPI D-PHY Channel B Data Lane 0; data rate up to 1.5 Gbps.
DB0N	5	I	MIPI D-PHY Channel B Data Lane 0; data rate up to 1.5 Gbps.
DB1P	6	I	MIPI D-PHY Channel B Data Lane 1; data rate up to 1.5 Gbps.
DB1N	7	I	MIPI D-PHY Channel B Data Lane 1; data rate up to 1.5 Gbps.
DBCP	8	I	MIPI D-PHY Channel B Clock Lane; operates up to 750 MHz.
DBCN	9	I	MIPI D-PHY Channel B Clock Lane; operates up to 750 MHz.
DB2P	10	I	MIPI D-PHY Channel B Data Lane 2; data rate up to 1.5 Gbps.
DB2N	11	I	MIPI D-PHY Channel B Data Lane 2; data rate up to 1.5 Gbps.
DB3P	12	I	MIPI D-PHY Channel B Data Lane 3; data rate up to 1.5 Gbps.
DB3N	13	I	MIPI D-PHY Channel B Data Lane 3; data rate up to 1.5 Gbps.
ML0P	37	O	DisplayPort Lane 0 transmit differential pair. Supports 1.62Gbps, 2.16Gbps, 2.43Gbps, 2.7Gbps, 3.24Gbps, 4.32Gbps, and 5.4Gbps. All DisplayPort lanes transmit at the same data rate.
ML0N	38	O
ML1P	39	O	DisplayPort Lane 1 transmit differential pair. Supports 1.62Gbps, 2.16Gbps, 2.43Gbps, 2.7Gbps, 3.24Gbps, 4.32Gbps, and 5.4Gbps. All DisplayPort lanes transmit at the same data rate.
ML1N	40	O
ML2P	44	O	DisplayPort Lane 2 transmit differential pair. Supports 1.62Gbps, 2.16Gbps, 2.43Gbps, 2.7Gbps, 3.24Gbps, 4.32Gbps, and 5.4Gbps. All DisplayPort lanes transmit at the same data rate.
ML2N	45	O
ML3P	46	O	DisplayPort Lane 3 transmit differential pair. Supports 1.62Gbps, 2.16Gbps, 2.43Gbps, 2.7Gbps, 3.24Gbps, 4.32Gbps, and 5.4Gbps. All DisplayPort lanes transmit at the same data rate.
ML3N	47	O
AUXP	34	I/O	Aux Channel Differential Pair.
AUXN	35	I/O	Aux Channel Differential Pair.
TEST1	60	I PD	Test Mode. When high, the SN65DSIx6 enters Test Mode. This pin should be left unconnected or tied to ground for normal operation.
TEST2	55	I/O PD	Used for internal test, HBR2 Compliance Eye, and Symbol Error Rate Measurement pattern. For normal operation, this pin should be pull-down to ground or left unconnected. Refer to DP Training and Compliance patterns for information on HBR2 Compliance Eye and Symbol Error Rate Measurement patterns.
TEST3	50	I	Used for Texas Instruments internal use only. This pin must be left unconnected or tied to ground through a 0.1µF capacitor.
GPIO1	58	I/O	General Purpose I/O. Refer to General Purpose Input and Outputs for details on GPIO functionality. When these pins are set high, they should be tied to the same 1.8V power rail where SN65DSIx6 VCCIO 1.8V power rail is connected.
GPIO2	56
GPIO3	54
GPIO4	57
HPD	32	I PD	HPD Input. This input requires an 51K 1% series resistor.
ADDR	1	I	Local I2C Interface Target Address Select. In normal operation, this pin is an input. When the ADDR pin is programmed high, it should be tied to the same 1.8V power rails where the SN65DSIx6 VCCIO 1.8V power rail is connected.
EN	2	I PU	Chip Enable and Reset. Device is reset (shutdown) when EN is low.
REFCLK	51	I	REFCLK. Frequency determined by value programmed in I2C register or value of GPIO[3:1] latched at rising edge of EN. Supported frequencies are: 12MHz, 19.2MHz, 26MHz, 27MHz, and 38.4MHz. This pin must be tied to or pulled down to ground when DACP/N feeds the DisplayPort PLL.
SCL	15	I	Local I2C Interface Clock
SDA	16	I/O	Local I2C Interface Data
IRQ	61	O	Interrupt Signal
GND	23, 26, 52, 64, Thermal pad	G	Reference Ground
VCCA	3, 14, 18, 31, 36, 41, 43, 48	P	1.2V Power Supply for Analog Circuits. VCCA and VCC must be applied simultaneously.
VCC	17, 33, 49, 59, 62	P	1.2V Power Supply for digital core
VPLL	42	P	1.8V Power Supply for DisplayPort PLL
VCCIO	53, 63	P	1.8V Power Supply for Digital I/O.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	V_CCA, V_CC	–0.3	1.3	V
Supply voltage	V_CCIO, V_PLL	–0.3	2.175	V
Input voltage	All input terminals	–0.5	2.175	V
Operating temperature		–40	85	°C
Storage temperature, T_stg		–65	105	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

				MIN	MAX	UNIT
T_stg	Storage temperature range			–65	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002 Classification Level H2, all pins⁽¹⁾		–2000	2000	V
		Charged device model (CDM), per AEC Q100-011 Classification Level C4B	Corner pins	–750	750
			Other pins	–500	500

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN			NOM	MAX	UNIT
V_CCA	VCCA Power supply; analog circuits	1.14	1.2	1.26	V
V_CC	VCC Power supply; digital circuits	1.14	1.2	1.26	V
V_CCIO	VCCIO Power Supply; digital IOs.	1.65	1.8	1.98	V
V_PLL	VPLL Power Supply, DisplayPort PLL	1.65	1.8	1.98	V
V_PSN	Supply noise on any VCC terminal	f_(noise)> 1 MHz		0.05	V
V_{DSI_PIN}	DSI input pin voltage range	–50		1350	mV
f_(I2C)	Local I²C input frequency			400	kHz
f_{HS_CLK}	DSI HS clock input frequency	40		750	MHz
Z_L	DP output differential load impedance	90		110	Ω
T_A	Operating free-air temperature	–40		85	°C
T_J	Operating junction temperature	–40		105	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		SN65DSI86-Q1	UNIT
		PAP
		64 TERMINALS
R_θJA	Junction-to-ambient thermal resistance	35.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	17.7	°C/W
R_θJB	Junction-to-board thermal resistance	19.5	°C/W
ψ_JT	Junction-to-top thermal resistance metric (High-K board⁽¹⁾)	0.7	°C/W
ψ_JB	Junction-to-board thermal resistance metric (High-K board⁽¹⁾)	19.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
STANDARD IO (TEST1, TEST2, ADDR, SCL, SDA, IRQ, REFCLK, EN, GPIO[4:1])
V_IL	Low-level control signal input voltage				0.3 × V_CCIO	V
V_IH	High-level control signal input voltage		0.7 × V_CCIO			V
V_OH	High-level output voltage	I_OH = –2 mA	1.3			V
V_OL	Low-level output voltage	I_OL = 2 mA			0.4	V
I_IH	High-level input current	Any input terminal			±5	μA
I_IL	Low-level input current	Any input terminal			±5	μA
I_OZ	High-impedance output current	Any output terminal			±10	μA
I_OS	Short-circuit output current	Any output driving GND short			±2	mA
I_CCA	V_CCA device active current	V_CCA = 1.2 V ⁽²⁾		70	126	mA
I_CC	V_CC device active current	V_CCA = 1.2 V ⁽²⁾		43	52	mA
I_CCIO	V_CCIO and V_PLL device active current	V_CCIO = 1.8 V, V_PLL = 1.8 V ⁽²⁾		32	32	mA
I_{SUSPEND_CCA}	V_CCA device suspend current	All data and clock lanes are in ultra-low power state (ULPS) and SUSPEND = 1		9.8		mA
I_{SUSPEND_CC}	V_CC device suspend current	All data and clock lanes are in ultra-low power state (ULPS) and SUSPEND = 1		9		mA
I_{SUSPEND_CCIO}	V_CCIO and V_PLL device suspend current	All data and clock lanes are in ultra-low power state (ULPS) and SUSPEND = 1		1.16		mA
I_{EN_CCA}	V_CCA shutdown current	EN = 0		0.95		mA
I_{EN_CC}	V_CCshutdown current	EN = 0		2		mA
I_{EN_CCIO}	V_CCIO and V_PLL shutdown current	EN = 0		0.038		mA
R_EN	EN control input resistor			150		kΩ
ADDR, EN, SCL, SDA, DBP/N[3:0], DAP/N[3:1], DBCP/N, DACP/N
I_LEAK	Input failsafe leakage current	V_CC= 0; V_CCIO = 0 V. Input pulled up to V_CCIO max. DSI inputs pulled up to 1.3 V	–40		40	µA
MIPI DSI INTERFACE
V_IH-LP	LP receiver input high threshold	See Figure 5	880			mV
V_IL-LP	LP receiver input low threshold	See Figure 5			550	mV
V_OH-LP	LP transmitter high-level output voltage		1100		1300	mV
V_OL-LP	LP transmitter low-level output voltage		–50		50	mV
V_IHCD	LP Logic 1 contention threshold		450			mV
V_ILCD	LP Logic 0 contention threshold				200	mV
\|V_ID\|	HS differential input voltage		70		270	mV
\|V_IDT\|	HS differential input voltage threshold				50	mV
V_IL-ULPS	LP receiver input low threshold; ultra-low power state (ULPS)				300	mV
V_CM-HS	HS common mode voltage; steady-state		70		330	mV
ΔV_CM-HS	HS common mode peak-to-peak variation including symbol delta and interference				100	mV
V_IH-HS	HS single-ended input high voltage	See Figure 5			460	mV
V_IL-HS	HS single-ended input low voltage	See Figure 5	–40			mV
V_TERM-EN	HS termination enable; single-ended input voltage (both Dp AND Dn apply to enable)	Termination is switched simultaneous for Dn and Dp			450	mV
R_DIFF-HS	HS mode differential input impedance		80		125	Ω
DisplayPort MAIN LINK
V_{TX_DC_CM}	Output common mode voltage		0		2	V
V_{TX_AC_CM_HBR_RBR}	TX AC common mode voltage for HBR and RBR.				20	mVRMS
V_{TX_AC_CM_HBR2}	TX AC common mode voltage for HBR2				30	mVRMS
V_{TX_DIFFPP_LVL0}	Differential peak-to-peak output voltage level 0	Based on default state of V0_P0_VOD register	300	400	460	mV
V_{TX_DIFFPP_LVL1}	Differential peak-to-peak output voltage level 1	Based on default state of V1_P0_VOD register	450	600	690	mV
V_{TX_DIFFPP_LVL2}	Differential peak-to-peak output voltage level 2	Based on default state of V2_P0_VOD register	600	800	920	mV
V_{TX_DIFFPP_LVL3}	Differential peak-to-peak output voltage level 3	Based on default state of V3_P0_VOD register. Level 3 is not enabled by default	600	800	920	mV
V_{TX_PRE_RATIO_0}	Pre-emphasis level 0		0	0	0	dB
V_{TX_PRE_RATIO_1}	Pre-emphasis level 1		2.8	3.5	4.2	dB
V_{TX_PRE_RATIO_2}	Pre-emphasis level 2		4.8	6.0	7.2	dB
V_{TX_PRE_RATIO_3}	Pre-emphasis level 3	Level 3 is not enabled by default	4.8	6.0	7.2	dB
V_{TX_PRE_POST2_RATIO_0}	Post-cursor2 level 0		0	0	0	dB
V_{TX_PRE_POST2_RATIO_1}	Post-cursor2 level 1		–1.1	–0.9	–0.7	dB
V_{TX_PRE_POST2_RATIO_2}	Post-cursor2 level 2		–2.3	–1.9	–1.5	dB
V_{TX_PRE_POST2_RATIO_3}	Post-cursor2 level 3	Level 3 is not enabled by default	–3.7	–3.1	–2.5	dB
I_{TX_SHORT}	TX short circuit current limit				50	mA
R_{TX_DIFF}	Differential impedance		80	100	120	Ω
C_{AC_COUPLING}	AC coupling capacitor		75		200	nF
DisplayPort HPD
V_{HPD_PLUG}	Hot plug detection threshold	Measured at 51-kΩ series resistor.	2.2			V
V_{HPD_UNPLUG}	Hot unplug detection threshold	Measured at 51-kΩ series resistor.			0.8	V
RHPDPD	HPD internal pulldown resistor		51	60	69	kΩ
DisplayPort AUX INTERFACE
V_{AUX_DIFF_PP_TX}	Peak-to-peak differential voltage at transmit pins	V_{AUX_DIFF_PP} = 2 × \|V_AUXP – V_AUXN\|	0.18		1.38	V
V_{AUX_DIFF_PP_RX}	Peak-to-peak differential voltage at receive pins	V_{AUX_DIFF_PP} = 2 × \|V_AUXP – V_AUXN\|	0.18		1.36	V
R_{AUX_TERM}	AUX channel termination DC resistance			100		Ω
V_{AUX_DC_CM}	AUX channel DC common mode voltage		0		1.2	V
V_{AUX_TURN_CM}	AUX channel turnaround common-mode voltage				0.3	V
I_{AUX_SHORT}	AUX Channel short circuit current limit				90	mA
C_AUX	AUX AC-coupling capacitor		75		200	nF

(1) All typical values are at V_CC = 1.2 V, V_CCA = 1.2 V, V_CCIO = 1.8 V, and V_PLL = 1.8 V, and T_A = 25°C

(2) Maximum condition: WQXGA 60 fps Dual-Link 2xDP at HBR2, PLL enabled; typical condition: WUXGA 60 fps 1xDP at HBR2, PLL enabled

7.6 Timing Requirements

		MIN	MAX	UNIT
Power-up For DPPLL_CLK_SRC = REFCLK, See Figure 1
td1	V_CC/A stable before V_CCIO/V_PLL stable	0		µs
td2	V_CC/A and V_CCIO/V_PLL stable before EN assertion	100		µs
td3	REFCLK active and stable before EN assertion	0		µs
td4	GPIO[3:1] stable before EN assertion	0		ns
td5	GPIO[3:1] stable after EN assertion	5		µs
td6	LP11 state on DSI channels A and B before EN assertion	0		ns
td7	LP11 state on DSI channels A and B after EN assertion⁽¹⁾	100		µs
t_{VCC_RAMP}	V_CCsupply ramp requirements	0.2	100	ms
t_{VCCA_RAMP}	V_CCAsupply ramp requirements	0.2	100	ms
t_{VCCIO_RAMP}	V_CCIO supply ramp requirements	0.2	100	ms
t_{VPLL_RAMP}	V_PLL supply ramp requirements	0.2	100	ms
Power-up For DPPLL_CLK_SRC = DACP/N, See Figure 2
td1	V_CC/A stable before V_CCIO/V_PLLstable	0		µs
td2	V_CC/A and V_CCIO/V_PLL stable before EN assertion	100		µs
td3	REFCLK low before EN assertion	10		µs
td4	GPIO[3:1] stable before EN assertion	0		ns
td5	GPIO[3:1] stable after EN assertion	5		µs
td6	LP11 state on DSI channels A and B before EN assertion	0		ns
td7	LP11 state on DSI channels A and B after EN assertion⁽¹⁾	100		µs
td8	DACP/N active and stable before DP_PLL_EN bit is set.	100		µs
t_{VCC_RAMP}	V_CCsupply ramp requirements	0.2	100	ms
t_{VCCA_RAMP}	V_CCAsupply ramp requirements	0.2	100	ms
t_{VCCIO_RAMP}	V_CCIO supply ramp requirements	0.2	100	ms
t_{VPLL_RAMP}	V_PLL supply ramp requirements	0.2	100	ms
SUSPEND Timing Requirements, See Figure 3
td1	LP11 or ULPS on DSI channel A and B before assertion of SUSPEND.	200		ns
td2	Delay from SUSPEND asserted to DisplayPort Main Link powered off.	2 × t_REFCLK
td3	REFCLK active hold time after assertion of SUSPEND	4 × t_REFCLK
td4	REFCLK active setup time before deassertion of SUSPEND.	100		ns
td5	Delay from SUSPEND deasserted to DisplayPort Main Link active and transmitting IDLE pattern. Semi-Auto Link Training is NOT used.		20 + (1155 × t_REFCLK)	µs
td6	LP11 state or ULPS on DSI channels A and B after SUSPEND deassertion	20 + (1155 × t_REFCLK)		µs

(1) Access to DSIx6 CFR from I²C or DSI allowed after td7.

7.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
MIPI DSI INTERFACE
t_GS	DSI LP glitch suppression pulse width				300	ps
t_HS-SETUP	DSI HS data to clock setup time		0.2			UI
t_HS-HOLD	DSI HS clock to data hold time		0.2			UI
DisplayPort MAIN LINK
F_BR7	Bit rate 7		5.37138	5.4	5.40162	Gbps
F_BR6	Bit rate 6		4.297104	4.32	4.321296	Gbps
F_BR5	Bit rate 5		3.222828	3.24	3.240972	Gbps
F_BR4	Bit rate 4		2.68569	2.7	2.70081	Gbps
F_BR3	Bit rate 3		2.417121	2.43	2.430729	Gbps
F_BR2	Bit rate 2		2.148552	2.16	2.160648	Gbps
F_BR1	Bit rate 1		1.611414	1.62	1.620486	Gbps
UI_BR7	Unit interval for BR7	High limit = +300 ppm. Low limit = –5300 ppm		185		ps
UI_BR6	Unit interval for BR6	High limit = +300 ppm. Low limit = –5300 ppm		231.5		ps
UI_BR5	Unit interval for BR5	High limit = +300 ppm. Low limit = –5300 ppm		308.6		ps
UI_BR4	Unit interval for BR4	High limit = +300 ppm. Low limit = –5300 ppm		370.4		ps
UI_BR3	Unit interval for BR3	High limit = +300 ppm. Low limit = –5300 ppm		411.5		ps
UI_BR2	Unit interval for BR2	High limit = +300 ppm. Low limit = –5300 ppm		463		ps
UI_BR1	Unit interval for BR1	High limit = +300 ppm. Low limit = –5300 ppm		617.3		ps
t_{ERC_L0}	Differential output rise or fall time with DP_ERC set to 0		50	61	80	ps
t_{ERC_L1}	Differential output rise or fall time with DP_ERC set to 1		74	95	115	ps
t_{ERC_L2}	Differential output rise or fall time with DP_ERC set to 2		108	123	146	ps
t_{ERC_L3}	Differential output rise or fall time with DP_ERC set to 3		136	153	168	ps
t_{TX_RISE_FALL} _{_MISMATCH}	Lane intra-pair output skew at TX pins				5%
t_{INTRA_SKEW}	Intra-pair differential skew				20	ps
t_{INTER_SKEW}	Inter-pair differential skew				100	ps
t_{TX_EYE_HBR2}	Minimum TX eye width at TX package pins for HBR2⁽²⁾		0.73			UI_HBR2
t_{TX_EYE_MED_TO} _{_MAX_JIT_HBR2}	Maximum time between the jitter median and maximum deviation from the median at TX package pins for HBR2⁽²⁾				0.135	UI_HBR2
t_{TX_EYE_HBR}	Minimum TX eye width at TX package pins for HBR⁽²⁾		0.72			UI_HBR
t_{TX_EYE_MED_TO} _{_MAX_JIT_HBR}	Maximum time between the jitter median and maximum deviation from the median at TX package pins for HBR⁽²⁾				0.147	UI_HBR
t_{TX_EYE_RBR}	Minimum TX eye width at TX package pins for RBR⁽²⁾		0.82			UI_RBR
t_{TX_EYE_MED_TO} _{_MAX_JIT_RBR}	Maximum time between the jitter median and maximum deviation from the median at TX package pins for RBR⁽²⁾				0.09	UI_RBR
t_{XSSC_AMP}	Link clock down-spreading		0%		0.5%
t_{SSC_FREQ}	Link clock down-spreading frequency		30		33	kHz
DisplayPort AUX INTERFACE
UI_MAN	Manchester transaction unit interval		0.4		0.6	µs
t_{auxjitter_tx}	Cycle-to-cycle jitter time at transmit pins				0.08	UI_MAN
t_{auxjitter_rx}	Cycle-to-cycle jitter time at receive pins				0.04	UI_MAN
REFCLK
f_REFCLK	REFCLK frequency. supported frequencies: 12 MHz, 19.2 MHz, 26 MHz, 27 MHz, 38.4 MHz		12		38.4	MHz
t_RISEFALL	REFCLK rise or fall time	10% to 90%	100 ps		23	ns
t_REFCLK	REFCLK period		26.0417		83.333	ns
t_pj	REFCLK peak-to-peak phase jitter				50	ps
Duty	REFCLK duty cycle		40%	50%	60%

(1) All typical values are at V_CC = 1.2 V and T_A = 25 °C

(2) BR refers to BR1; HBR refers to BR; HBR2 refers to BR7.

SN65DSI86-Q1 pow_up_tim_REFCLK2_SLLSEH2.gif

Figure 1. Power-Up Timing Definitions for DPPLL_CLK_SRC = REFCLK

SN65DSI86-Q1 pow_up_tim_DACPN_SLLSEH2.gif

Figure 2. Power-Up Timing Definitions for DPPLL_CLK_SRC = DACP/N

Figure 3. SUSPEND Timing Definitions

Figure 4. DSI HS Mode Receiver Timing Definitions

Figure 5. DSI Receiver Voltage Definitions