SLLSEJ5A July   2014  – December 2015 SN65DSI86-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 MIPI Dual DSI Interface
      2. 8.3.2 Embedded DisplayPort Interface
      3. 8.3.3 General-Purpose Input and Outputs
        1. 8.3.3.1 GPIO REFCLK and DSIA Clock Selection
        2. 8.3.3.2 Suspend Mode
        3. 8.3.3.3 Pulse Width Modulation (PWM)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset Implementation
      2. 8.4.2 Power-Up Sequence
      3. 8.4.3 Power Down Sequence
      4. 8.4.4 Display Serial Interface (DSI)
        1. 8.4.4.1 DSI Lane Merging
        2. 8.4.4.2 DSI Supported Data Types
        3. 8.4.4.3 Generic Request Datatypes
          1. 8.4.4.3.1 Generic Read Request 2-Parameters Request
          2. 8.4.4.3.2 Generic Short Write 2-Parameters Request
          3. 8.4.4.3.3 Generic Long Write Packet Request
        4. 8.4.4.4 DSI Pixel Stream Packets
        5. 8.4.4.5 DSI Video Transmission Specifications
        6. 8.4.4.6 Video Format Parameters
        7. 8.4.4.7 GPU LP-TX Clock Requirements
      5. 8.4.5 DisplayPort
        1. 8.4.5.1  HPD (Hot Plug/Unplug Detection)
        2. 8.4.5.2  AUX_CH
          1. 8.4.5.2.1 Native Aux Transactions
        3. 8.4.5.3  I2C-Over-AUX
          1. 8.4.5.3.1 Direct Method (Clock Stretching)
          2. 8.4.5.3.2 Indirect Method (CFR Read/Write)
        4. 8.4.5.4  DisplayPort PLL
        5. 8.4.5.5  DP Output VOD and Pre-emphasis Settings
        6. 8.4.5.6  DP Main Link Configurability
        7. 8.4.5.7  DP Main Link Training
          1. 8.4.5.7.1 Manual Link Training
          2. 8.4.5.7.2 Fast Link Training
          3. 8.4.5.7.3 Semi-Auto Link Training
          4. 8.4.5.7.4 Redriver Semi-Auto Link Training
        8. 8.4.5.8  Panel Size vs DP Configuration
        9. 8.4.5.9  Panel Self Refresh (PSR)
        10. 8.4.5.10 Secondary Data Packet (SDP)
        11. 8.4.5.11 Color Bar Generator
        12. 8.4.5.12 DP Pattern
          1. 8.4.5.12.1 HBR2 Compliance Eye
          2. 8.4.5.12.2 80-Bit Custom Pattern
        13. 8.4.5.13 BPP Conversion
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface Overview
    6. 8.6 Register Map
      1. 8.6.1 Standard CFR Registers (PAGE 0)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 1080p (1920x1080 60 Hz) Panel
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 eDP Design Procedure
          2. 9.2.1.2.2 DSI Design Procedure
          3. 9.2.1.2.3 Example Script
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCCA Power supply
    3. 10.3 VPLL and VCCIO Power Supplies
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DSI Guidelines
      2. 11.1.2 eDP Guidelines
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

To minimize the power supply noise floor, provide good decoupling near the SN65DSIx6 power pins. The use of four ceramic capacitors (2 × 0.1 μF and 2 × 0.1 μF) provides good performance. At the very least, TI recommends to install one 0.1-μF and one 0.01-μF capacitors near the SN65DSIx6. To avoid large current loops and trace inductance, the trace length between decoupling capacitor and device power inputs pins must be minimized. Placing the capacitor underneath the SN65DSIx6 on the bottom of the PCB is often a good choice.
Note: The power supplies VPLL, VCCIO, VCCA, and VCC can be applied simultaneously.

11.1.1 DSI Guidelines

  1. DA*P/N and DB*P/N pairs should be routed with controlled 100-Ω differential impedance (± 20%) or 50-Ω single-ended impedance (±15%).
  2. Keep away from other high speed signals.
  3. Keep lengths to within 5 mils of each other.
  4. Length matching should be near the location of mismatch. See Figure 4 for an example.
  5. Each pair should be separated at least by 3 times the signal trace width.
  6. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥ 135°. This arrangement minimizes any length mismatch caused by the bends and therefore minimizes the impact that bends have on EMI.
  7. Route all differential pairs on the same of layer.
  8. The number of VIAS should be kept to a minimum. TI recommends to keep the VIAS count to 2 or less.
  9. Keep traces on layers adjacent to ground plane.
  10. Do NOT route differential pairs over any plane split.
  11. Adding Test points will cause impedance discontinuity and will therefore negatively impact signal performance. If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes a stub on the differential pair.
  12. The maximum trace length over FR4 between SN65DSI86 and the GPU is 25 to 30 cm.

11.1.2 eDP Guidelines

  1. ML*P/N pairs should be routed with controlled 100-Ω differential impedance (± 20%) or 50-Ω single-ended impedance (± 15%).
  2. Keep away from other high speed signals.
  3. Keep lengths to within 5 mils of each other.
  4. Length matching should be near the location of mismatch. See Figure 4 for an example.
  5. Each pair should be separated at least by 3 times the signal trace width.
  6. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥ 135°. This arrangement minimizes any length mismatch caused by the bends and therefore minimizes the impact that bends have on EMI
  7. Route all differential pairs on the same of layer.
  8. The number of VIAS should be kept to a minimum. TI recommends to keep the VIAS count to 2 or less.
  9. Keep traces on layers adjacent to ground plane.
  10. Do NOT route differential pairs over any plane split.
  11. Adding Test points will cause impedance discontinuity and will therefore negatively impact signal performance. If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes a stub on the differential pair.
  12. The maximum trace length over FR4 between SN65DSIx6 and the eDP receptacle is 4 inches for data rates less than or equal to HBR (2.7 Gbps) and 2 inches for HBR2 (5.4 Gbps).

11.1.3 Ground

TI recommends that only one board ground plane be used in the design. This provides the best image plane for signal traces running above the plane. The thermal pad of the SN65DSIx6 should be connected to this plane with vias.

11.2 Layout Example

SN65DSI86-Q1 layout_SLLSEJ5.gif