SLLS550E November   2002  – March 2023 SN65HVD08 , SN75HVD08

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Driver Switching Characteristics
    7. 6.7 Receiver Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Supply Source Impedance
      2. 9.1.2 Opto-Isolated Data Buses
      3. 9.1.3 Opto Alternative
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
          1.        30
          2.        31
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4 Device Functional Modes

Table 8-1 Function Table: Driver
INPUTENABLEOUTPUTS
DDEAB
H
L
X
Open		H
H
L
H		H
L
Z
H		L
H
Z
L
Table 8-2 Function Table: Receiver
DIFFERENTIAL INPUTSENABLE(1)OUTPUT(1)
VID = VA - VBRER
VID≤ -0.2 V
-0.2 V < VID < -0.01 V
-0.01 V ≤ VID
X
Open Circuit
Short Circuit		L
L
L
H
L
L		L
?
H
Z
H
H
(1) H = high level; L = low level; Z = high impedance; X = irrelevant;
? = indeterminate
GUID-13E31ECD-5632-4AAC-944D-60E75815842E-low.gifFigure 8-2 Equivalent Input and Output Schematic Diagrams