12.1 Layout Guidelines

• Use a 4-layer board with Layer 1 (top layer) for control signals, Layer 2 as Power Ground Layer for L– and GND), Layer 3 for the 24 V supply plane (L+), and Layer 4 for the regulated output supply (V_{CC_OUT}).
• Use entire planes for L+, V_{CC_OUT}, and L– and GND to assure minimum inductance during fast load or transient current changes.
• The L+ terminal must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended capacitor value is 1 μF to 4.7 μF. The capacitor must have a voltage rating of 50 V minimum and a X5R or X7R dielectric.
• The optimum placement is closest to the transceiver’s L+ and L– terminals to reduce supply drops during large supply current loads. See Figure 19 for a PCB layout example
• Place TVS diode close to the connector to prevent the transient energy from entering the circuitry.
• Use two vias when connecting TVS diodes or capacitors to the L– and L+ planes to maintain low inductance during fast load or transient current changes.
• Connect all open-drain control outputs and the receiver output via 10 kΩ pull-up resistors to the V_{CC_OUT} plane to provide a defined voltage potential to the system controller inputs when the outputs are high-impedance.
• Connect the transceiver enable pin via a 10 kΩ pull-down resistor to ground, to assure the driver output is disabled during power-up.
• Connect V_{CC_SET} directly to ground to make V_{CC_OUT} = 3.3 V, or leave it open to make V_{CC_OUT} = 5 V.
• Connect V_{CC_IN} directly to V_{CC_OUT} to assure proper voltage regulation.
• Buffer the regulated output voltage at V_{CC_OUT} to ground with a low-ESR, 3.3μF, ceramic bypass-capacitor. The capacitor should have a voltage rating of 10 V minimum and a X5R or X7R dielectric.

12.2 Layout Example

Figure 19. Layout Example