SLLS631E April   2007  – August 2015 SN65HVD1040

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Driver Electrical Characteristics
    6. 7.6  Receiver Electrical Characteristics
    7. 7.7  Device Switching Characteristics
    8. 7.8  Driver Switching Characteristics
    9. 7.9  Receiver Switching Characteristics
    10. 7.10 Dissipation Ratings
    11. 7.11 Supply Current
    12. 7.12 Split-Pin Characteristics
    13. 7.13 STB-Pin Characteristics
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Mode Control
        1. 9.3.1.1 High-Speed Mode
        2. 9.3.1.2 Low-Power Mode
      2. 9.3.2 Dominant State Time-Out
      3. 9.3.3 Thermal Shutdown
      4. 9.3.4 SPLIT
      5. 9.3.5 Operating Temperature Range
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Bus Loading, Length, and Number of Nodes
        2. 10.2.1.2 CAN Termination
        3. 10.2.1.3 Loop Propagation Delay
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 CAN Basics
          1. 10.2.2.1.1 Differential Signal
          2. 10.2.2.1.2 Common-Mode Signal
          3. 10.2.2.1.3 ESD Protection
          4. 10.2.2.1.4 Transient Voltage Suppresser (TVS) Diodes
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Parameter Measurement Information

SN65HVD1040 dv_cur_lls631.gifFigure 11. Driver Voltage, Current, and Test Definition
SN65HVD1040 bus_svd_lls631.gifFigure 12. Bus Logic State Voltage Definitions
SN65HVD1040 drv_tcir_lls631.gifFigure 13. Driver VOD Test Circuit
SN65HVD1040 drv_tc_vw_lls631.gifFigure 14. Driver Test Circuit and Voltage Waveforms
SN65HVD1040 recv_cvw_lls631.gifFigure 15. Receiver Voltage and Current Definitions
SN65HVD1040 rectc_vw_lls631.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR  ≤ 125 kHz, 50% duty cycle, tr  ≤ 6 ns, tf  ≤ 6ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.
Figure 16. Receiver Test Circuit and Voltage Waveforms

Table 1. Differential Input Voltage Threshold Test

INPUT OUTPUT
VCANH VCANL |VID| R
–11.1 V –12 V 900 mV L VOL
12 V 11.1 V 900 mV L
–6 V –12 V 6 V L
12 V 6 V 6 V L
–11.5 V –12 V 500 mV H VOH
12 V 11.5 V 500 mV H
–12 V –6 V 6 V H
6 V 12 V 6 V H
Open Open X H
SN65HVD1040 ten_cir_vwf_lls631.gifFigure 17. Ten Test Circuit and Voltage Waveforms
SN65HVD1040 ptp_vo_twf_lls631.gif
All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 18. Peak-To-Peak Common Mode Output Voltage Test and Waveform
SN65HVD1040 tloop_twf_lls631.gif
All VI input pulses are from 0 V to VCC and supplied by a generator with the following characteristics: tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 19. Tloop Test Circuit and Voltage Waveforms
SN65HVD1040 to_twf_lls631.gif
All VI input pulses are from 0 V to VCC and supplied by a generator with the following characteristics: tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 500 Hz, 50% duty cycle.
A. CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
Figure 20. Dominant Time-Out Test Circuit and Waveform
SN65HVD1040 tbus_twf_lls631.gif
A. For VI bit width ≤ 0.7 μs, VO = VOH. For VII bit width ≥ 5 μs, VO = VOL. VI input pulses are supplied from a generator with the following characteristics; tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 50 Hz, 30% duty cycle.
B. CL = 15 pF includes instrumentation and fixture capacitance within ±20%.
Figure 21. TBUS Test Circuit and Waveform
SN65HVD1040 dsc_twf_lls631.gifFigure 22. Driver Short-Circuit Current Test and Waveform
SN65HVD1040 outsymt_lls631.gifFigure 23. Driver Output Symmetry Test Circuit