SLLS632C December   2005  – February 2015 SN65HVD1050

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Driver Electrical Characteristics
    6. 7.6  Receiver Electrical Characteristics
    7. 7.7  Device Switching Characteristics
    8. 7.8  Driver Switching Characteristics
    9. 7.9  Receiver Switching Characteristics
    10. 7.10 Supply Current
    11. 7.11 S-Pin Characteristics
    12. 7.12 VREF-Pin Characteristics
    13. 7.13 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Mode Control
        1. 9.3.1.1 Normal Mode
        2. 9.3.1.2 Silent Mode
      2. 9.3.2 TXD Dominant Timeout (DTO)
      3. 9.3.3 Thermal Shutdown
      4. 9.3.4 VREF
      5. 9.3.5 Operating Temperature Range
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Bus Loading, Length, and Number of Nodes
        2. 10.2.1.2 CAN Termination
          1. 10.2.1.2.1 Loop Propagation Delay
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ESD Protection
        2. 10.2.2.2 Transient Voltage Suppresser (TVS) Diodes
      3. 10.2.3 Application Curve
    3. 10.3 System Example
      1. 10.3.1 ISO 11898 Compliance of SN65HVD1050 5-V CAN Transceiver
        1. 10.3.1.1 Introduction
        2. 10.3.1.2 Differential Signal
        3. 10.3.1.3 Common-Mode Signal
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Parameter Measurement Information

SN65HVD1050 dvr_tst_lls632.gif
Figure 11. Driver Voltage, Current, and Test Definition
SN65HVD1050 vod_tst_lls632.gif
Figure 13. Driver VOD Test Circuit
SN65HVD1050 bus_log_lls632.gif
Figure 12. Bus Logic State Voltage Definitions
SN65HVD1050 drv_tst_wf_lls632.gifFigure 14. Driver Test Circuit and Voltage Waveforms
SN65HVD1050 rx_v_cd_lls632.gifFigure 15. Receiver Voltage and Current Definitions
SN65HVD1050 rx_tst_wf_lls632.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.
Figure 16. Receiver Test Circuit and Voltage Waveforms

Table 1. Differential Input Voltage Threshold Test

INPUT OUTPUT
VCANH VCANL |VID| R
–11.1V –12V 900 mV L VOL
12V 11.1V 900 mV L
–6V –12V 6V L
12V 6V 6V L
–11.5V –12V 500 mV H VOH
12V 11.5V 500 mV H
–12V –6V 6V H
6V 12V 6V H
Open Open X H
SN65HVD1050 ten_tc_wf_lls632.gifFigure 17. TEN Test Circuit and Waveform
SN65HVD1050 comonmode_lls632.gif

NOTE:

All VI input pulses are from 0V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 18. Common Mode Output Voltage Test and Waveforms
SN65HVD1050 tloop_tc_wf_lls632.gif
A. All VI input pulses are from 0V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 19. T(LOOP) Test Circuit and Waveform
SN65HVD1050 tm_out_wf_lls632.gif
A. All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 500 Hz, 50% duty cycle.
B. CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
Figure 20. Dominant Time-Out Test Circuit and Waveforms
SN65HVD1050 drv_sc_wf_lls632.gifFigure 21. Driver Short-Circuit Current Test and Waveform