SLLS563I July   2003  – January 2023 SN65HVD1176 , SN75HVD1176

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Supply Current
    7. 6.7 Power Dissipation
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
      1.      Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
        4. 8.2.1.4 Receiver Failsafe
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
    3. 11.3 Related Links
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
DRIVER
VOOpen-circuit output voltageA or BNo load0VCCV
|VOD(SS)|Steady-state differential output voltage magnitudeRL = 54 ΩSee Figure 7-12.12.9V
With common-mode loading,
(VTEST from –7 V to 12 V)
See Figure 7-2		2.12.7V
Δ|VOD(SS)|Change in steady-state differential output voltage between logic statesSee Figure 7-1 and Figure 7-6–0.200.2V
VOC(SS)Steady-state common-mode output voltageSee Figure 7-522.53V
ΔVOC(SS)Change in steady-state common-mode output voltageSee Figure 7-5–0.200.2V
VOC(PP)Peak-to-peak common-mode output voltageSee Figure 7-50.5V
VOD(RING)Differential output voltage over and under shootRL = 54 Ω, CL = 50 pF
See Figure 7-6		10%VOD(PP)
IIInput currentD, DE–5050μA
IOS(P)Peak short-circuit output currentDE at VCC,
See Figure 7-8		VOS = –7 V to 12 V–250250mA
IOS(SS)Steady-state short-circuit output currentDE at VCC,
See Figure 7-8		VOS > 4 V,
Output driving low		6090135mA
VOS < 1 V,
Output driving high		–135–90–60mA
RECEIVER
VIT(+)Positive-going differential input voltage thresholdSeeFigure 7-9VO = 2.4 V, IO = –8 mA–80–20mV
VIT(–)Negative-going differential input voltage thresholdVO = 0.4 V, IO = 8 mA–200–120mV
VHYSHysteresis voltage (VIT+ – VIT-)40mV
VOHHigh-level output voltageVID = 200 mV, IOH = –8 mA,
See Figure 7-9		44.6V
VOLLow-level output voltageVID = –200 mV, IOL = 8 mA,
See Figure 7-9		0.20.4V
IA, IBBus pin input currentVI = –7 V to 12 V,
Other input = 0 V		VCC = 4.75 V to 5.25 V–160200μA
IA(OFF)
IB(OFF)		VCC = 0 V–160200
IIReceiver enable input currentRE–5050μA
IOZHigh-impedance - state output currentRE = VCC–11μA
RIInput resistance60kΩ
CIDDifferential input capacitanceTest input signal is a 1.5-MHz sine wave with amplitude 1 VPP, capacitance measured across A and B710pF
CMRCommon mode rejectionSee Figure 7-114V
(1) All typical values are at VCC = 5 V and 25°C.