SLLSEJ8E June   2014  – April 2019 SN65HVD1470 , SN65HVD1471 , SN65HVD1473 , SN65HVD1474 , SN65HVD1476 , SN65HVD1477

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions — SOIC-8 and MSOP-8
    2.     Pin Functions — MSOP–10
    3.     Pin Functions — SOIC-14
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information — D Packages
    5. 7.5  Thermal Information — DGS and DGK Packages
    6. 7.6  Power Dissipation
    7. 7.7  Electrical Characteristics
    8. 7.8  Switching Characteristics — 400 kbps
    9. 7.9  Switching Characteristics — 20 Mbps
    10. 7.10 Switching Characteristics — 50 Mbps
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Equivalent Circuits
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1.      Master Enable Control
      2.      Slave Enable Control
      3. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
        4. 10.2.1.4 Receiver Failsafe
        5. 10.2.1.5 Transient Protection
      4. 10.2.2 Detailed Design Procedure
      5. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.9 Switching Characteristics — 20 Mbps

20-Mbps devices (SN65HVD1473, SN65HVD1474) bit time ≥ 50 ns (over recommended operating conditions)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRIVER
tr, tf Driver differential output rise/fall time RL = 54 Ω, CL = 50 pF See Figure 17 4 7 14 ns
tPHL, tPLH Driver propagation delay 4 10 20 ns
tSK(P) Driver pulse skew, |tPHL – tPLH| 0 4 ns
tPHZ, tPLZ Driver disable time HVD1473 See Figure 18 and Figure 19 12 25 ns
tPZH, tPZL Driver enable time Receiver enabled 10 20 ns
Receiver disabled 3 8 µs
RECEIVER
tr, tf Receiver output rise/fall time CL = 15 pF See Figure 20 5 10 ns
tPHL, tPLH Receiver propagation delay time 60 90 ns
tSK(P) Receiver pulse skew, |tPHL – tPLH| 0 5 ns
tPLZ, tPHZ Receiver disable time HVD1473 17 25 ns
tpZL(1), tPZH(1) tPZL(2), tPZH(2) Receiver enable time Driver enabled See Figure 21 12 90 ns
Driver disabled See Figure 22 3 8 µs