SLLSE49E September   2010  – October 2024 SN65HVD1780-Q1 , SN65HVD1781-Q1 , SN65HVD1782-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings—AEC
    3. 5.3  ESD Ratings—IEC
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Power Dissipation Ratings
    8. 5.8  Switching Characteristics
    9. 5.9  Package Dissipation Ratings
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bus Fault Conditions
      2. 7.3.2 Receiver Failsafe
      3. 7.3.3 Hot-Plugging
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Bus Loading
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stub Length
        2. 8.2.2.2 Receiver Failsafe
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Supply voltage 3.15 5 5.5 V
VI Input voltage at any bus terminal (separately or common mode)(1) –7 12 V
VIH High-level input voltage (driver, driver enable, and receiver enable inputs) 2 VCC V
VIL Low-level input voltage (driver, driver enable, and receiver enable inputs) 0 0.8 V
VID Differential input voltage –12 12 V
IO Output current, driver –60 60 mA
Output current, receiver –8 8 mA
RL Differential load resistance 54 60 Ω
CL Differential load capacitance 50 pF
1/tUI Signaling rate SN65HVD1780-Q1 0.115 Mbps
SN65HVD1781-Q1 1
SN65HVD1782-Q1 10
TA Operating free-air temperature (See the Thermal Information table) 5V supply –40 105 °C
3.3V supply –40 125
TJ Junction Temperature –40 150 °C
(1) By convention, the least positive (most negative) limit is designated as minimum in this data sheet.