SLLSF08A May   2017  – February 2022 SN65HVD1781A-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC
    3. 6.3 ESD Ratings—IEC
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Power Dissipation Ratings
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Receiver Failsafe
      2. 8.3.2 Hot-Plugging
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Bus Loading
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Stub Length
        2. 9.2.2.2 Receiver Failsafe
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
|VOD|Driver differential output voltage magnitudeRL = 60 Ω, 4.75 V ≤ VCC 375 Ω
on each output to –7 V to 12 V, See Figure 7-1		TA < 85°C1.5V
TA < 125°C1.4
RL = 54 Ω,
4.75 V ≤ VCC ≤ 5.25 V		TA < 85°C1.72
TA < 125°C1.5
RL = 54 Ω,
3.15 V ≤ VCC ≤ 3.45 V		0.81
RL = 100 Ω,
4.75 V ≤ VCC ≤ 5.25 V		TA < 85°C2.22.5
TA < 125°C2
Δ|VOD|Change in magnitude of driver differential output voltageRL = 54 Ω–50050mV
VOC(SS)Steady-state common-mode output voltage1VCC/23V
ΔVOCChange in differential driver output common-mode voltage–50050mV
VOC(PP)Peak-to-peak driver common-mode output voltageCenter of two 27-Ω load resistors,
See Figure 7-2		500mV
CODDifferential output capacitance23pF
VIT+Positive-going receiver differential input voltage threshold–100–35mV
VIT–Negative-going receiver differential input voltage threshold–180–150mV
VHYSReceiver differential input voltage threshold hysteresis
(VIT+ – VIT–)(1)		3050mV
VOHReceiver high-level output voltageIOH = –8 mA2.4VCC – 0.3V
VOLReceiver low-level output voltageIOL = 8 mATA < 85°C0.20.4V
TA < 125°C0.5
II(LOGIC)Driver input, driver enable, and receiver enable input current–5050μA
IOZReceiver output high-impedance currentVO = 0 V or VCC, RE at VCC–11μA
IOSDriver short-circuit output current–200200mA
II(BUS)Bus input current (disabled driver)VCC = 3.15 to 5.5 V or
VCC = 0 V, DE at 0 V		VI = 12 V75100μA
VI = –7 V–60–40
ICCSupply current (quiescent)Driver and receiver enabledDE = VCC, RE = GND,
no load		46mA
Driver enabled, receiver disabledDE = VCC, RE = VCC,
no load		35
Driver disabled, receiver enabledDE = GND, RE = GND,
no load		24
Driver and receiver disabled, standby modeDE = GND, D = open,
RE = VCC, no load, TA < 85°C		0.151μA
DE = GND, D = open,
RE = VCC, no load, TA < 125°C		12
Supply current (dynamic)See the Section 6.9 section
(1) Ensured by design. Not production tested.