SLLSF08A May   2017  – February 2022 SN65HVD1781A-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC
    3. 6.3 ESD Ratings—IEC
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Power Dissipation Ratings
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Receiver Failsafe
      2. 8.3.2 Hot-Plugging
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Bus Loading
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Stub Length
        2. 9.2.2.2 Receiver Failsafe
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
DRIVER
tr, tfDriver differential output rise/fall timeRL = 54 Ω, CL = 50 pF, See Figure 7-350300ns
tPHL, tPLHDriver propagation delayRL = 54 Ω, CL = 50 pF, See Figure 7-3200ns
tSK(P)Driver differential output pulse skew,
|tPHL – tPLH|		RL = 54 Ω, CL = 50 pF, See Figure 7-325ns
tPHZ, tPLZDriver disable timeSee Figure 7-4 and Figure 7-53μs
tPZH, tPZLDriver enable timeReceiver enabledSee Figure 7-4 and Figure 7-5300ns
Receiver disabled10μs
RECEIVER
tr, tfReceiver output rise/fall time (1)CL = 15 pF,
See Figure 7-6		415ns
tPHL, tPLHReceiver propagation delay timeCL = 15 pF,
See Figure 7-6		100200ns
tSK(P)Receiver output pulse skew,
|tPHL – tPLH|		CL = 15 pF,
See Figure 7-6		620ns
tPLZ, tPHZReceiver disable time (1)Driver enabled, See Figure 7-715100ns
tPZL(1), tPZH(1)
tPZL(2), tPZH(2)		Receiver enable timeDriver enabled, See Figure 7-780300ns
Driver disabled, See Figure 7-839μs
(1) Specified by design. Not production tested.