SLLSF08A May   2017  – February 2022 SN65HVD1781A-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC
    3. 6.3 ESD Ratings—IEC
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Power Dissipation Ratings
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Receiver Failsafe
      2. 8.3.2 Hot-Plugging
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Bus Loading
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Stub Length
        2. 9.2.2.2 Receiver Failsafe
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.2 Receiver Failsafe

The differential receivers of the SN65HVD1781A-Q1 has receiver input thresholds that are offset so that receiver output state is known for the following three fault conditions:

  • Open bus conditions, such as a disconnected connector
  • Shorted bus conditions, such as cable damage shorting the twisted-pair together
  • Idle bus conditions that occur when no driver on the bus is actively driving

In any of these cases, the differential receiver will output a failsafe logic High state so that the output of the receiver is not indeterminate.

Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input VID is more positive than 200 mV, and must output a Low when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are VIT(+), VIT(–), and VHYS (the separation between VIT(+) and VIT(–)). As shown in the Section 6.6 table, differential signals more negative than –200mV will always cause a Low receiver output, and differential signals more positive than 200 mV will always cause a High receiver output.

When the differential input signal is close to zero, it is still above the maximum VIT(+) threshold of –35 mV, and the receiver output will be High. Only when the differential input is more than VHYS below VIT(+) will the receiver output transition to a Low state. Therefore, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis value, VHYS, as well as the value of VIT(+).

GUID-24CAAFD4-415A-4610-A6D6-F76D971B55D8-low.gifFigure 9-5 Noise Immunity Under Bus Fault Conditions