SLLS545G November   2002  – October 2015 SN55HVD251 , SN65HVD251

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Supply Current
    6. 6.6  Electrical Characteristics: Driver
    7. 6.7  Electrical Characteristics: Receiver
    8. 6.8  VREF-Pin Characteristics
    9. 6.9  Power Dissipation Characteristics
    10. 6.10 Switching Characteristics: Driver
    11. 6.11 Switching Characteristics: Device
    12. 6.12 Switching Characteristics: Receiver
    13. 6.13 Dissipation Ratings
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Mode Control
      2. 8.3.2 High-Speed Mode
      3. 8.3.3 Slope Control Mode
      4. 8.3.4 Low-Power Mode
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Bus Loading, Length, and Number of Nodes
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CAN Termination
        2. 9.2.2.2 Loop Propagation Delay
      3. 9.2.3 Application Curve
    3. 9.3 System Example
      1. 9.3.1 ISO 11898 Compliance of HVD251 5-V CAN Bus Transceiver
        1. 9.3.1.1 Introduction
        2. 9.3.1.2 Differential Signal
        3. 9.3.1.3 Common-Mode Signal
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

SN55HVD251 SN65HVD251 DrvVCurTst_lls545.gif Figure 10. Driver Voltage, Current, and Test Definition
SN55HVD251 SN65HVD251 BusLog_lls545.gif Figure 11. Bus Logic State Voltage Definitions
SN55HVD251 SN65HVD251 DrvV_lls545.gif Figure 12. Driver VOD
SN55HVD251 SN65HVD251 DrvTestCrcVO_lls545.gif Figure 13. Driver Test Circuit and Voltage Waveforms
SN55HVD251 SN65HVD251 RcvVltCureceiver.gif Figure 14. Receiver Voltage and Current Definitions
SN55HVD251 SN65HVD251 RcvTestCirc_lls545.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.
Figure 15. Receiver Test Circuit and Voltage Waveforms
SN55HVD251 SN65HVD251 TstCircTrans_lls545.gif
This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 16. Test Circuit, Transient Overvoltage Test

Table 1. Receiver Characteristics Over Common Mode Voltage

INPUT DIFFERENTIAL INPUT OUTPUT
VCANH VCANL |VID| R
12 V 11.1 V 900 mV L VOL
–6.1 V –7 V 900 mV L
–1 V –7 V 6 V L
12 V 6 V 6 V L
–6.5 V –7 V 500 mV H VOH
12 V 11.5 V 500 mV H
–7 V –1 V 6 V H
6 V 12 V 6 V H
open open X H
SN55HVD251 SN65HVD251 TeTstCircVlt_lls545.gif Figure 17. Ten Test Circuit and Voltage Waveforms
SN55HVD251 SN65HVD251 Pk2PkCMOut_lls545.gif
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO = 50 Ω.
Figure 18. Peak-to-Peak Common Mode Output Voltage
SN55HVD251 SN65HVD251 TloopTstCirc_lls545.gif Figure 19. TLOOP Test Circuit and Voltage Waveforms
SN55HVD251 SN65HVD251 DrvShrtCircT_lls545.gif Figure 20. Driver Short-Circuit Test
SN55HVD251 SN65HVD251 RcvPrpDlySdb_lls545.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.
Figure 21. Receiver Propagation Delay in Standby Test Circuit and Waveform
SN55HVD251 SN65HVD251 CMVI_lls545.gif
A. All input pulses are supplied by a generator having the following characteristics: fIN < 1.5 MHz, TA = 25°C, VCC = 5 V.
B. The receiver output should not change state during application of the common-mode input waveform.
Figure 22. Common-Mode Input Voltage Rejection Test