SLLSEA2D December 2011 – May 2015 SN65HVD255 , SN65HVD256 , SN65HVD257
PRODUCTION DATA.
This CAN transceiver meets the ISO1189-2 High Speed CAN (Controller Area Network) Physical Layer standard. It is designed for data rates in excess of
1 Mbps for CAN in short networks, and enhanced timing margin and higher data rates in long and highly-loaded networks. The device provides many protection features to enhance device and CAN-network robustness. The SN65HVD257 device adds additional features, allowing for easy design of redundant and multitopology networks with fault indication for higher levels of functional safety in the CAN system.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN65HVD255 SN65HVD256 SN65HVD257 |
SOIC (8) | 4.90 mm × 3.91 mm |
Changes from C Revision (September 2013) to D Revision
Changes from B Revision (June 2012) to C Revision
Changes from A Revision (June 2012) to B Revision
Changes from * Revision (December 2011) to A Revision
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Supply voltage | –0.3 | 6.1 | V | |
VRXD | RXD Output supply voltage | SN65HVD256 | –0.3 | 6 and VRXD ≤ VCC + 0.3 | V |
VBUS | CAN Bus I/O voltage (CANH, CANL) | –27 | 40 | V | |
VLogic_Input | Logic input pin voltage (TXD, S) | –0.3 | 6 | V | |
VLogic_Output | Logic output pin voltage (RXD) | SN65HVD255, SN65HVD257 | –0.3 | 6 | V |
VLogic_Output | Logic output pin voltage (RXD) | SN65HVD256 | –0.3 | 6 and VI ≤ VRXD + 0.3 | V |
IO(RXD) | RXD (Receiver) output current | 12 | mA | ||
IO(FAULT) | FAULT output current | SN65HVD257 | 20 | mA | |
TJ | Operating virtual junction temperature (see Power Dissipation) | –40 | 150 | °C | |
TA | Ambient temperature (see Power Dissipation) | –40 | 125 | °C |
VALUE | UNIT | |||||
---|---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | All pins | ±2500 | V | |
CAN bus pins (CANH, CANL)(2) | ±12000 | |||||
Charged-device model (CDM), per JEDEC specification JESD22-C101(3) | All pins | ±750 | ||||
Machine model | All pins | ±250 | ||||
IEC 61400-4-2 according to GIFT-ICT CAN EMC test spec(4) | CAN bus pins (CANH, CANL) to GND | ±8000 | ||||
ISO7637 Transients according to GIFT - ICT CAN EMC test spec(5) | CAN bus pins (CANH, CANL) | Pulse 1 | –100 | |||
Pulse 2 | +75 | |||||
Pulse 3a | –150 | |||||
Pulse 3b | +100 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Supply voltage | 4.5 | 5.5 | V | |
VRXD | RXD supply (SN65HVD256 only) | 2.8 | 5.5 | ||
VI or VIC | CAN bus terminal voltage (separately or common mode) | –2 | 7 | ||
VID | CAN bus differential voltage | -6 | 6 | ||
VIH | Logic HIGH level input (TXD, S) | 2 | 5.5 | ||
VIL | Logic LOW level input (TXD, S) | 0 | 0.8 | ||
IOH(DRVR) | CAN BUS Driver High level output current | –70 | mA | ||
IOL(DRVR) | CAN BUS Driver Low level output current | 70 | |||
IOH(RXD) | RXD pin HIGH level output current | –2 | |||
IOL(RXD) | RXD pin LOW level output current | 2 | |||
IO(FAULT) | FAULT pin LOW level output current | SN65HVD257 | 2 | ||
TA | Operational free-air temperature (see Power Dissipation) | –40 | 125 | °C |
THERMAL METRIC(1) | SN65HVD25x | UNIT | |
---|---|---|---|
D (SOIC) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance, High-K thermal resistance(2) | 107.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 56.7 | °C/W |
RθJB | Junction-to-board thermal resistance | 48.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 12.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 48.2 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SUPPLY CHARACTERISTICS | |||||||
ICC | 5-V Supply current | Normal Mode (Driving Dominant) | See Figure 6, TXD = 0 V, RL = 50 Ω, CL = open, RCM = open, S = 0 V |
60 | 85 | mA | |
Normal Mode (Driving Dominant – bus fault) | See Figure 6, TXD = 0 V, S = 0 V, CANH = –12 V, RL = open, CL = open, RCM = open |
130 | 180 | ||||
Normal Mode (Driving Dominant) | See Figure 6, TXD = 0 V, RL = open (no load), CL = open, RCM = open, S = 0 V |
10 | 20 | ||||
Normal Mode (Recessive) | See Figure 6, TXD = VCC, RL = 50 Ω, CL = open, RCM = open, S = 0 V |
10 | 20 | ||||
Silent Mode | See Figure 6, TXD = VCC, RL = 50 Ω, CL = open, RCM = open, S = VCC |
2.5 | 5 | ||||
IRXD | RXD Supply current (SN65HVD256 only) | All modes | RXD Floating, TXD = 0 V | 500 | µA | ||
UVVCC | Undervoltage detection on VCC for protected mode | 3.5 | 4.45 | V | |||
VHYS(UVVCC) | Hysteresis voltage on UVVCC | 200 | mV | ||||
UVRXD | Undervoltage detection on VRXD for protected mode (SN65HVD256 only) | 1.3 | 2.75 | V | |||
VHYS(UVRXD) | Hysteresis voltage on UVRXD (SN65HVD256 only) | 80 | mV | ||||
S PIN (MODE SELECT INPUT) | |||||||
VIH | HIGH-level input voltage | 2 | V | ||||
VIL | LOW-level input voltage | 0.8 | V | ||||
IIH | HIGH-level input leakage current | S = VCC = 5.5 V | 7 | 100 | µA | ||
IIL | Low-level input leakage current | S = 0 V, VCC = 5.5 V | –1 | 0 | 1 | µA | |
ILKG(OFF) | Unpowered leakage current | S = 5.5 V, VCC = 0 V, VRXD = 0 V | 7 | 35 | 100 | µA | |
TXD PIN (CAN TRANSMIT DATA INPUT) | |||||||
VIH | HIGH level input voltage | 2 | V | ||||
VIL | LOW level input voltage | 0.8 | V | ||||
IIH | HIGH level input leakage current | TXD = VCC = 5.5 V | –2.5 | 0 | 1 | µA | |
IIL | Low level input leakage current | TXD = 0 V, VCC = 5.5 V | –100 | –25 | –7 | µA | |
ILKG(OFF) | Unpowered leakage current | TXD = 5.5 V, VCC = 0 V, VRXD = 0 V | –1 | 0 | 1 | µA | |
CI | Input Capacitance | 3.5 | pF | ||||
RXD PIN (CAN RECEIVE DATA OUTPUT) | |||||||
VOH | HIGH level output voltage | See Figure 7, IO = –2 mA. For devices with VRXD supply VOH = 0.8 × VRXD | 0.8 × VCC | V | |||
VOL | LOW level output voltage | See Figure 7, IO = 2 mA | 0.4 | V | |||
ILKG(OFF) | Unpowered leakage current | RXD = 5.5 V, VCC = 0 V, VRXD = 0 V | –1 | 0 | 1 | µA | |
DRIVER ELECTRICAL CHARACTERISTICS | |||||||
VO(D) | Bus output voltage (dominant) | CANH | See Figure 15 and Figure 6, TXD = 0 V, S = 0 V, RL = 60 Ω, CL = open, RCM = open |
2.75 | 4.5 | V | |
CANL | 0.5 | 2.25 | |||||
VO(R) | Bus output voltage (recessive) | See Figure 15 and Figure 6, TXD = VCC, VRXD = VCC, S = VCC or 0 V (2), RL = open (no load), RCM = open | 2 | 0.5 × VCC | 3 | V | |
VOD(D) | Differential output voltage (dominant) | See Figure 15 and Figure 6, TXD = 0 V, S = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = 330 Ω, –2 V ≤ VCM ≤ 7 V, 4.75 V≤ VCC ≤ 5.25 V |
1.5 | 3 | V | ||
See Figure 15 and Figure 6, TXD = 0 V, S = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = 330 Ω, –2 V ≤ VCM ≤ 7 V, 4.5 V ≤ VCC ≤ 5.5 V |
1.25 | 3.2 | |||||
VOD(R) | Differential output voltage (recessive) | See Figure 15 and Figure 6, TXD = VCC, S = 0 V, RL = 60 Ω, CL = open, RCM = open |
–0.12 | 0.012 | V | ||
See Figure 15 and Figure 6, TXD = VCC, S = 0 V, RL = open (no load), CL = open, RCM = open, –40°C ≤ TA ≤ 85°C |
–0.100 | 0.050 | |||||
VSYM | Output symmetry (dominant or recessive) (VCC – VO(CANH) – VO(CANL)) |
See Figure 15 and Figure 6, S at 0 V, RL = 60 Ω, CL = open, RCM = open |
–0.4 | 0.4 | V | ||
IOS(SS)_DOM | Short circuit steady-state output current, Dominant | See Figure 15 and Figure 11, VCANH = 0 V, CANL = open, TXD = 0 V | –160 | mA | |||
See Figure 15 and Figure 11, VCANL = 32 V, CANH = open, TXD = 0 V |
160 | ||||||
IOS(SS)_REC | Short circuit steady-state output current, Recessive | See Figure 15 and Figure 11, –20 V ≤ VBUS ≤ 32 V, Where VBUS = CANH = CANL, TXD = VCC, Normal and Silent Modes |
–8 | 8 | mA | ||
CO | Output capacitance | See Input capacitance to ground (CI) in the following Receiver Electrical Characteristics section of this table | |||||
RECEIVER ELECTRICAL CHARACTERISTICS | |||||||
VIT+ | Positive-going input threshold voltage, normal mode | See Figure 7, Table 5 and Table 1 | 900 | mV | |||
VIT– | Negative-going input threshold voltage, normal mode | 500 | mV | ||||
VHYS | Hysteresis voltage (VIT+ - VIT–) | 125 | mV | ||||
IIOFF(LKG) | Power-off (unpowered) bus input leakage current | VCANH = VCANL = 5 V, VCC = 0 V, VRXD = 0 V |
5.5 | µA | |||
CI | Input capacitance to ground (CANH or CANL) | TXD = VCC, VRXD = VCC, VI = 0.4 sin (4E6 π t) + 2.5 V |
25 | pF | |||
CID | Differential input capacitance | TXD = VCC, VRXD = VCC, VI = 0.4 sin (4E6 π t) |
10 | pF | |||
RID | Differential input resistance | TXD = VCC = VRXD = 5 V, S = 0 V | 30 | 80 | kΩ | ||
RIN | Input resistance (CANH or CANL) | 15 | 40 | kΩ | |||
RIN(M) | Input resistance matching: [1 – RIN(CANH) / RIN(CANL)] × 100% |
V(CANH) = V(CANL), –40°C ≤ TA ≤ 85°C | –3% | 3% | |||
FAULT PIN (FAULT OUTPUT), SN65HVD257 ONLY | |||||||
ICH | Output current high level | FAULT = VCC, see Figure 5 | –10 | 10 | µA | ||
ICL | Output current low level | FAULT = 0.4 V, see Figure 5 | 5 | 12 | mA |
THERMAL METRIC | TEST CONDITIONS | TYP | UNIT | |
---|---|---|---|---|
PD | Average power dissipation | VCC = 5 V, VRXD = 5 V, TJ = 27°C, RL = 60 Ω, S at 0 V, Input to TXD at 250 kHz, 25% duty cycle square wave, CL_RXD = 15 pF. Typical CAN operating conditions at 500 kbps with 25% transmission (dominant) rate. | 115 | mW |
VCC = 5.5 V, VRXD = 5.5 V, TJ = 150°C, RL = 50 Ω, S at 0 V, Input to TXD at 500 kHz, 50% duty cycle square wave, CL_RXD = 15 pF. Typical high load CAN operating conditions at 1 Mbps with 50% transmission (dominant) rate and loaded network. | 268 | |||
Thermal shutdown temperature | 170 | °C | ||
Thermal shutdown hysteresis | 5 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DEVICE SWITCHING CHARACTERISTICS | ||||||
tPROP(LOOP1) | Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant | See Figure 9, S = 0 V, RL = 60 Ω, CL = 100 pF, CL_RXD = 15 pF |
150 | ns | ||
tPROP(LOOP2) | Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive | 150 | ||||
IMODE | Mode change time, from Normal to Silent or from Silent to Normal | See Figure 8 | 20 | µS | ||
DRIVER SWITCHING CHARACTERISTICS | ||||||
tpHR | Propagation delay time, HIGH TXD to Driver Recessive | See Figure 6, S = 0 V, RL = 60 Ω, CL = 100 pF, RCM = open |
50 | 70 | ns | |
tpLD | Propagation delay time, LOW TXD to Driver Dominant | 40 | 70 | |||
tsk(p) | Pulse skew (|tpHR – tpLD|) | 10 | ||||
tR | Differential output signal rise time | 10 | 30 | |||
tF | Differential output signal fall time | 17 | 30 | |||
tR(10k) | Differential output signal rise time, RL = 10 kΩ |
See Figure 6, S = 0 V, RL = 10 kΩ, CL = 10 pF, RCM = open |
35 | ns | ||
tF(10k) | Differential output signal fall time, RL = 10 kΩ |
100 | ||||
tTXD_DTO | Dominant timeout(1) | See Figure 10, RL = 60 Ω, CL = open | 1175 | 3700 | µs | |
RECEIVER SWITCHING CHARACTERISTICS | ||||||
tpRH | Propagation delay time, recessive input to high output | See Figure 7, CL_RXD = 15 pF | 70 | 90 | ns | |
tpDL | Propagation delay time, dominant input to low output | 70 | 90 | ns | ||
tR | Output signal rise time | 4 | 20 | ns | ||
tF | Output signal fall time | 4 | 20 | ns | ||
tRXD_DTO(2) | Receiver dominant time out (SN65HVD257 only) See Figure 4, CL_RXD = 15 pF | 1380 | 4200 | µs |